Pipeline Level-Crossing ADC for Adaptive Continuous-Time Sampling
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Solution Overview
Problem
Conventional digital signal processing systems suffer from limitations such as high signal processing activity due to discrete time sampling, frequency aliasing, aliased noise, and analog nonlinearities, leading to inefficiencies in neural networks and software defined radios.
Innovation Solution
A continuous time signal processing subsystem with N stages, each stage receiving reference levels and outputting error values, using scaled reference voltage levels to minimize overlapping crossings and employing a summing circuit for digital output, and a continuous time pipeline level-crossing ADC architecture that avoids analog mixers and corrects for timing and amplitude errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional discrete time sampling is used, then signal processing can be performed, but the number of samples is high and energy consumption increases
Solution Approach 1:
The patent implements adaptive sampling where the sampling rate dynamically adjusts based on signal activity. When signal slope is low, sampling rate decreases; when signal slope is high, sampling rate increases. This dynamic adaptation reduces the total number of samples while maintaining signal fidelity, directly addressing the energy consumption vs. productivity contradiction.
Solution Approach 2:
The system changes the sampling parameter (sampling rate) based on signal characteristics. By monitoring signal slope and adjusting the sampling interval accordingly, the system optimizes the balance between processing workload and energy consumption, resolving the contradiction between high sample count and energy efficiency.
2Measurement precision
If conventional pipeline ADC is used, then analog-to-digital conversion is achieved, but multiple simultaneous state changes cause timing and amplitude errors
Solution Approach 1:
The patent segments the conversion process into distinct stages with non-overlapping reference levels. Each stage handles specific voltage ranges with dedicated reference levels, preventing simultaneous state changes across multiple stages. This segmentation eliminates timing and amplitude errors while maintaining conversion accuracy.
Solution Approach 2:
The patent introduces an intermediary mechanism (level crossing detection with non-overlapping references) that mediates between the analog input and digital output. This intermediary ensures that only one state change occurs at a time, resolving the timing and amplitude errors caused by simultaneous transitions in conventional pipeline ADCs.
3Speed
If conventional flash ADC is used, then high conversion speed is achieved, but the number of comparators grows exponentially
Solution Approach 1:
The patent divides the flash ADC into multiple stages, each handling a portion of the voltage range. This segmentation reduces the number of comparators required in each stage from exponential growth to linear scaling, while maintaining high conversion speed through parallel processing within each stage.
Solution Approach 2:
The patent transitions from a single-stage exponential architecture to a multi-stage hierarchical architecture. By adding the dimension of multiple stages with cascaded processing, the system achieves high speed conversion with reduced comparator count, resolving the contradiction between speed and complexity.
4Adaptability or versatility
If analog mixer is used in SDR, then frequency conversion is achieved, but nonlinearities and intermodulation distortion occur
Solution Approach 1:
The patent replaces the analog mixer (mechanical/electrical multiplication system) with a direct digital synthesis approach using lookup tables and phase accumulators. This substitution eliminates the nonlinearities and intermodulation distortion inherent in analog mixers while maintaining frequency conversion capability through digital processing.
Solution Approach 2:
The patent introduces digital intermediaries (phase accumulators, lookup tables, and digital signal processing blocks) that mediate between the input and output signals. These digital intermediaries perform frequency conversion without the nonlinearities of analog mixing, eliminating intermodulation distortion while preserving adaptability.
Data Source
AI summary
Continuous time pipeline, level-crossing (LC), analog-to-digital converters (ADCs) use a plurality of stages from a first stage to a last stage. Each stage has an array of comparators that are provided with an array of reference voltage levels. Each stage is configured to detect level crossings of increasing fineness compared to the preceding stage such that the accuracy of a digitized representation of an input signal can be increased by adding stages as well as increasing the number of comparators in each stage. The voltage error in the digitized representation of the signal that remains after each stage provides the input to the subsequent stage. The continuous time pipeline LC ADCs are also applied to analog signal processing and software defined radios.