Processor Pipeline Load-Store Fusion for Bus Width Utilization
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Solution Overview
Problem
Existing processor architectures inefficiently utilize the bandwidth between the processor and cache or memory due to load and store instructions that do not fully utilize the available bus width, leading to underutilization of the interface.
Innovation Solution
Identify patterns of multiple memory access instructions that reference a common base register and do not fully utilize the available bus width, and replace them with a single equivalent instruction that utilizes more of the available bus width, such as combining adjacent or non-contiguous memory access instructions into a single cache line operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple narrow memory access instructions are used to access memory, then the processor can maintain simple instruction encoding and decoding, but the bus width utilization is insufficient and bandwidth is wasted
Solution Approach 1:
The patent combines multiple narrow memory access instructions (e.g., multiple 32-bit load/store instructions) into a single wide memory access instruction (e.g., 128-bit load/store instruction) that can utilize the full bus width. This merging approach maintains instruction simplicity while improving bandwidth utilization by accessing multiple memory locations in a single operation.
Solution Approach 2:
The patent changes the parameter of memory access width from narrow (32-bit) to wide (128-bit) by detecting patterns of multiple memory access instructions and replacing them with equivalent wide instructions. This parameter change allows the processor to fully utilize the available bus width while maintaining the same functional effect of accessing multiple memory locations.
2Device complexity
If multiple memory access instructions are executed sequentially, then the processor pipeline can maintain simple instruction flow, but the overall execution time increases and throughput decreases
Solution Approach 1:
The patent merges multiple sequential memory access instructions into a single wide memory access instruction that can retrieve or store multiple data elements in one operation. This reduces the number of instructions in the pipeline, improves throughput, and maintains relatively simple pipeline structure by using standard instruction fusion techniques.
Solution Approach 2:
The patent performs preliminary analysis of instruction patterns to identify sequences of memory access instructions that can be combined. By detecting these patterns before execution and pre-computing the equivalent wide instruction, the processor can optimize throughput without adding complex runtime decision-making to the pipeline.
3Adaptability or versatility
If narrow memory access instructions are used, then the processor can maintain compatibility with existing instruction sets, but the interface bandwidth between processor and cache is underutilized
Solution Approach 1:
The patent changes the data transfer volume parameter by replacing multiple narrow instructions with a single wide instruction that transfers more data in one operation. The instruction set remains compatible through pattern-based translation, where sequences of existing narrow instructions are replaced with equivalent wide instructions that leverage the full interface bandwidth.
Solution Approach 2:
The patent makes the memory access instruction universal by creating a wide instruction format that can handle multiple data elements simultaneously. This single wide instruction replaces multiple narrow instructions, making the instruction set more versatile while maintaining compatibility through systematic substitution of instruction patterns.
Data Source
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AI summary
Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.