Pipeline Structure for Shared Memory Protocol Latency Reduction
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Solution Overview
Problem
In processor-based systems, especially mid-range server systems with multiple system boards, the broadcast method for accessing shared memory becomes inefficient as the number of boards grows, leading to increased latency and bandwidth issues due to high capacitance and inductance concerns, as well as the need for additional processing power to handle increased memory access requests.
Innovation Solution
Implementing a pipeline structure that allows for data transfer requests to be processed during subsequent clock cycles, reducing latency by using a pipeline protocol to perform at least a portion of the request immediately following the initial request, thereby improving bandwidth and reducing communication latency between system domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the broadcast method is used for accessing shared memory in a distributed system, then all system boards can receive memory access requests, but the latency increases and bandwidth is reduced as the number of system boards grows
Solution Approach 1:
The patent segments the monolithic broadcast approach into a hierarchical directory-based system where memory address space is divided into regions, each managed by a specific system board. This segmentation reduces the number of boards that need to be contacted for each memory access, thereby reducing latency while maintaining reliable access through the directory structure that guides requests to the appropriate target board.
Solution Approach 2:
The patent introduces a directory structure as an intermediary between the requesting system board and the target memory board. The directory contains mapping information that directs memory requests to the appropriate destination, eliminating the need for universal broadcasting and reducing access latency while ensuring reliable delivery through directed communication paths.
2Productivity
If the number of system boards is increased to improve system capacity, then processing power and memory resources increase, but the capacitance and inductance of the common bus increase causing electrical concerns and reduced performance
Solution Approach 1:
The patent extracts the common bus communication function and replaces it with a switched fabric interconnect system. This extraction removes the electrical interference problems associated with large-scale broadcast buses while maintaining the ability to connect increased numbers of system boards through point-to-point or point-to-multipoint connections that avoid the capacitance and inductance issues of shared broadcast media.
3Reliability
If directory caches are designed to hold mappings for all memory locations, then complete memory mapping is achieved, but significant memory overhead is required
Solution Approach 1:
The patent implements local quality by allowing each system board to maintain directory cache entries only for the memory address regions it manages or has cached. This selective directory caching approach provides complete mapping coverage across the distributed system while minimizing memory overhead at each individual board, as each board stores only the directory information relevant to its local memory management responsibilities.
4Productivity
If client/server communication is used between system boards, then targeted memory access is achieved, but inherent latency occurs during transactions between client and server boards
Solution Approach 1:
The patent applies preliminary action by pre-establishing directory cache mappings and maintaining information about memory location ownership and caching status before actual memory access transactions occur. This preliminary preparation allows the system to quickly determine the destination of memory requests and initiate direct targeted access, reducing transaction latency while maintaining efficient client/server communication between system boards.
Data Source
AI summary
A method and apparatus for implementation of a pipeline structure for data transfer. A request is received from a first domain to access a second domain during a first clock cycle. A pipeline structure is used to perform at least a portion of the request during a subsequent clock cycle.