Pipeline NOP Insertion for Shared Memory Access Synchronization

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Solution Overview

Problem

Pipeline processing efficiency is reduced due to synchronization displacement of data paths when shared memory is accessed, causing pipeline stalls and requiring restarts of partially executed instructions.

Innovation Solution

An instruction insertion controller is used to insert no-operation instructions or detect embedded no-operation instructions in the control program, allowing the pipeline processing unit to continue execution without interruption by correcting relative displacement of control information between stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the pipeline processing unit continues execution without stopping when shared memory is accessed, then processing efficiency is maintained, but data path synchronization displacement occurs causing hazards

Engineering Contradiction:
Improveprocessing efficiencyVSAvoiddata path synchronization
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The instruction insertion controller detects memory access requests from general-purpose processors before the pipeline completes its current instructions, and proactively inserts NOP instructions into the pipeline. This preliminary action prevents synchronization displacement hazards before they occur, allowing the pipeline to continue execution without full stalls while maintaining data path integrity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

NOP (no-operation) instructions serve as intermediary elements inserted into the pipeline instruction stream. These NOP instructions act as buffers that absorb the timing discrepancy between pipeline execution and external memory access, allowing data to be properly synchronized without stopping the entire pipeline. The NOP instructions fill the time gap without consuming computational resources.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the pipeline is stopped to allow shared memory access, then data synchronization is maintained, but processing efficiency deteriorates due to pipeline stalls and instruction restarts

Engineering Contradiction:
Improvedata path synchronizationVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system proactively inserts NOP instructions before the pipeline would naturally stall, allowing continuous execution flow. By preparing the pipeline with NOP placeholders in advance, the system avoids the overhead of detecting hazards, stopping, and restarting instructions, thereby maintaining high processing efficiency while ensuring data synchronization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pipeline processing unit maintains continuous operation by inserting NOP instructions that preserve the instruction flow. Instead of stopping the pipeline and losing the momentum of parallel processing, the NOP instructions allow the pipeline to continue advancing through its stages, keeping all processing units actively engaged and maintaining throughput.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If NOP instructions are inserted to accommodate memory access requests, then pipeline continuity is maintained, but control information displacement occurs between stages

Engineering Contradiction:
Improvepipeline throughputVSAvoidcontrol information management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The instruction insertion controller acts as an intermediary between the instruction fetch unit and the pipeline stages. It intercepts the instruction stream, inserts NOP instructions at appropriate locations, and manages the control information flow. This centralized control mechanism handles the complexity of tracking and adjusting control signals for inserted NOPs, preventing dispersion across multiple pipeline stages.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The instruction insertion controller monitors memory access requests from general-purpose processors and uses this feedback to determine where NOP instructions should be inserted. By continuously observing the timing and nature of external memory accesses, the controller dynamically adjusts the insertion points of NOP instructions, ensuring proper synchronization without manual intervention or complex pre-programming.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8200950B2Sharing pipeline by inserting NOP to accommodate memory access request received from other processors
Publication Date: 2012.06.12 KK TOSHIBA
  • US8200950B2 patent drawing
  • US8200950B2 patent drawing
  • US8200950B2 patent drawing

AI summary

A pipeline operation processor comprises a pipeline processing unit and an instruction insertion controller which inserts an instruction when access to an operation memory is requested, and corrects control information by reference to control information of stages. When a control program is in execution, on receiving an access request instruction requesting for access to the operation memory, the instruction insertion controller inserts an NOP instruction from the instruction decoding unit in place of the access request instruction. The access request instruction is executed while the pipeline processing unit executes no operation, and subsequently, the pipeline processing is continued.