Processor Pipeline Circuit With Register Bypass Selector
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Solution Overview
Problem
The introduction of registers in processor pipelines causes data transmission delays due to clock uncertainty and the need for on-chip variation margins, which hinders improved data throughput.
Innovation Solution
A circuit structure is introduced with a selector that bypasses the register, allowing direct data signal output via another input end while the register latches the signal, eliminating delays caused by clock uncertainty and on-chip variation margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If registers are introduced in processor pipeline to reduce logical depth, then processor performance is improved, but data transmission delay increases due to clock uncertainty and on-chip variation margins
Solution Approach 1:
The patent extracts the harmful function of the register (causing delay) while preserving its useful function (data storage). By separating the data transmission path from the register, the register's storage capability is maintained while its delay-causing effect is eliminated. The selector enables direct bypass of the register for data transmission, extracting only the necessary storage function.
Solution Approach 2:
The selector acts as an intermediary component between the data source and the register. It mediates the data flow by providing two paths: one through the register and one bypassing it. This intermediary enables flexible routing, allowing data to bypass the register when delay needs to be minimized while still maintaining the register's data storage capability when needed.
2Device complexity
If registers are used in pipeline implementation, then logical depth is reduced, but data transmission rate decreases due to register delay
Solution Approach 1:
The patent introduces dynamic routing capability through the selector, which can adaptively switch between two operational modes: bypass mode (for high-speed transmission) and register mode (for data storage). This dynamic switching allows the system to optimize between speed and storage needs based on real-time requirements, making the data path flexible rather than fixed.
Data Source
AI summary
A circuit structure includes a selector and a register. The selector includes a plurality of input ends, an output end, and a control end. A first input end in the plurality of input ends is configured to input a data signal, a second input end in the plurality of input ends is coupled to an output end of the register, and the output end of the selector is coupled to an input end of the register. The selector selectively transmits, to the output end of the selector based on a control signal input by the control end, a data signal input by the first input end or the data signal stored in the register.