Pipeline SAR ADC PVT Biasing for Stable Gain and Speed

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Solution Overview

Problem

Existing pipeline SAR ADCs are sensitive to Process, Voltage, and Temperature (PVT) variations, leading to instability in gain, offset, and speed, particularly in mobile communication networks, due to insufficient headroom margins and rapid temperature changes, which prior art methods fail to adequately address.

Innovation Solution

A PVT-dependent bias voltage is generated to stabilize the operating point of comparators and residual amplifiers, regulating the output common mode voltage and compensating for PVT variations by using a threshold voltage generator to maintain consistent gain and speed across varying conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If dynamic amplifiers are used for residual amplification in pipeline SAR ADC, then power consumption is reduced, but gain stability deteriorates due to sensitivity to PVT variations

Engineering Contradiction:

Improvepower consumptionVSAvoidgain stability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent changes the operating parameters of the dynamic amplifier by introducing a PVT-dependent bias voltage that adjusts the amplifier's gain characteristic. This allows the amplifier to maintain stable gain across PVT variations while operating in the dynamic mode, thus resolving the contradiction between low power consumption and gain stability.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the PVT-dependent bias voltage is generated based on detected PVT conditions and fed back to adjust the dynamic amplifier's operation. This feedback loop compensates for PVT variations in real-time, maintaining gain stability while preserving the low power consumption advantage of dynamic amplifiers.

Inventive Principle:

Principle #23Feedback

2Use of energy by moving object

If circuits are placed in sleep mode to reduce power consumption, then power efficiency improves, but temperature stability deteriorates due to rapid temperature rise upon activation

Engineering Contradiction:

Improvepower consumptionVSAvoidtemperature stability

Core Design Contradiction:

Use of energy by moving objectVSTemperature

Solution Approach 1:

The patent applies preliminary action by generating the PVT-dependent bias voltage in advance, before the circuit is activated from sleep mode. This bias voltage is prepared based on predicted or pre-measured PVT conditions, allowing the circuit to quickly establish stable operation without experiencing rapid temperature-induced gain variations during activation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the bias voltage parameter dynamically based on PVT conditions, allowing the circuit to adapt to temperature changes upon wake-up from sleep mode. This parameter adjustment compensates for thermal effects, maintaining stable gain even during rapid temperature transitions.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If redundancy is increased to compensate for RA gain variation, then gain stability improves, but device complexity increases

Engineering Contradiction:

Improvegain stabilityVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/approximate solution of using redundancy (multiple amplifiers or complex correction circuits) with an electronic solution based on PVT-dependent bias voltage generation. This substitution maintains gain stability through electronic compensation rather than structural redundancy, thereby reducing device complexity while preserving reliability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12456984B2PVT stabilization of pipelined SAR ADC

Publication Date: 2025.10.28 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

AI summary

In a pipelined Successive Approximation Register Analog to Digital Converter, SAR ADC, a Process, Temperature, and Voltage (PVT)-dependent bias voltage is generated and used to bias the inputs of comparators in at least the first SAR stage and residual amplifier (RA). This achieves a stable biasing and an operating point of the comparators and RA input stages that is independent of PVT variations, by tracking PVT variations in such a way that variations in MOS threshold voltage and drain-source voltage are counteracted. Additionally, a threshold common mode voltage is generated from the PVT-dependent voltage, which controls the amplification duration of the RAs such that the final RA output common mode voltage is substantially equal to the PVT-dependent voltage, which is used to bias the inputs of successive SAR stages. The threshold is set to account for logic delays in terminating the amplification based on the threshold comparison, to achieve the desired common mode amplifier output. The dependency on PVT of the threshold additionally cancels temperature variation from a differential stage transconductance of the RA. Further temperature stabilization is achieved by boosting the charge output by the RA to a capacitive load during part of the amplification.