Pipeline SAR ADC Gain Correction Without Speed Penalty
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Solution Overview
Problem
High-speed time-interleaved analog-to-digital converters (TIADCs) face challenges in maximizing operation speed due to the need for separate times for normal ADC operation and interstage gain error correction, which can burden the operation speed of single channels and increase power consumption.
Innovation Solution
A voltage-current domain pipeline successive approximation register (SAR) ADC separates the time for normal operation and gain correction, using a coarse ADC, an amplifier, a fine ADC, and an auxiliary path to generate gain correction signals independently of the fine ADC's operation time, allowing for background gain correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gain correction is performed during normal ADC operation, then measurement precision is improved, but operation speed deteriorates
Solution Approach 1:
The patent performs gain correction in advance during idle periods or before normal operation. The auxiliary path calculates gain correction values using test signals when the ADC is not processing main input signals, and stores these correction values for later application during normal operation, thus avoiding any impact on conversion speed
Solution Approach 2:
The patent separates the ADC system into a main conversion path and an auxiliary correction path. The auxiliary path includes dedicated components (test signal generator, auxiliary amplifier, correction value calculator) that operate independently from the main signal path, allowing gain correction to be performed without interfering with the primary conversion function
2Measurement precision
If gain correction circuit is added to correct interstage gain errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The auxiliary amplifier in the correction path uses the same gain setting as the main signal path amplifier. By adjusting the auxiliary amplifier's gain through the calculated correction value, the system corrects interstage gain errors without requiring separate correction circuits for each stage, thus reducing overall complexity
Solution Approach 2:
The patent introduces an auxiliary path as an intermediary system that generates correction values based on test signals. This intermediary path mediates between the main conversion path and the gain correction function, allowing correction to be achieved through software or digital processing rather than complex analog circuit modifications
3Productivity
If multiple ADC channels operate in parallel to increase conversion performance, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent implements time-interleaved operation where multiple ADC channels process different time segments of the input signal. Each channel operates continuously at a lower rate, and their results are combined to achieve high-speed conversion. This continuous operation at optimized rates reduces power consumption compared to having all channels operate at full speed simultaneously
Data Source
AI summary
An analog-to-digital converter (ADC) includes a coarse ADC that receives an analog input voltage, generates a first digital signal based on the analog input voltage using a successive approximation register (SAR) method, and outputs a residual voltage remaining after the first digital signal is generated. The ADC further includes an amplifier that receives the residual voltage and a test voltage, generates a residual current by amplifying the residual voltage by a predetermined gain, and generates a test current by amplifying the test voltage by the gain. The ADC further includes a fine ADC that receives the residual current and generates a second digital signal based on the residual current using the SAR method, and an auxiliary path that receives the test current and generates a gain correction signal based on the test current. The gain of the amplifier is adjusted based on the gain correction signal.