Pipeline Scheduler for Packet Switch Flow Control
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Solution Overview
Problem
Packet switches with credit-based flow control protocols face limitations in maximum packet throughput due to propagation delays in logic circuitry, especially when implementing ordering rules, which increase complexity and delay.
Innovation Solution
A pipeline scheduler with pipeline stages for credit update, request, and grant operations, along with an enqueue stage to manage packet requests and credits, allowing for faster scheduling and routing of packets based on available credits and ordering rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a credit-based flow control protocol is implemented in a single clock cycle scheduler, then flow control functionality is achieved, but propagation delays in logic circuitry increase and maximum packet throughput is constrained
Solution Approach 1:
The scheduler is divided into multiple pipeline stages (credit update stage, request stage, grant stage) that process different aspects of the scheduling function in sequence. Each stage operates at a lower complexity level, allowing the overall system to achieve higher throughput by processing multiple packets through different stages in parallel within a single clock cycle.
2Stability of the object's composition
If ordering rules are implemented to determine packet routing order, then packet ordering is maintained, but logic circuitry complexity increases and propagation delays are increased
Solution Approach 1:
The enqueue pipeline stage pre-processes packets by determining their routing order before the main scheduling decision is made. By establishing the enqueue order in advance based on ordering rules, the subsequent scheduling stages can operate more simply without having to re-evaluate packet order, thereby reducing overall logic complexity while maintaining ordering requirements.
3Extent of automation
If all scheduling functions are performed in a single clock cycle, then scheduling completeness is achieved, but clock frequency is constrained by propagation delays
Solution Approach 1:
The complete scheduling function is segmented into multiple pipeline stages that can operate in parallel. Each stage performs a specific sub-function (credit updating, request generation, grant allocation) and can process different packets simultaneously, allowing the system to maintain comprehensive scheduling functionality while operating at higher clock frequencies that would be impossible for a monolithic scheduler.
Data Source
AI summary
A packet switch includes a pipeline scheduler for scheduling packets according to a credit-based flow control protocol. A credit update pipeline stage initializes available credits for egress ports of the packet switch. A request pipeline stage generates packet requests for packets based on the available credits. A grant pipeline stage selects packets based on the ports requests and the available credits, and generates port grants for the selected packets. Additionally, the credit update stage updates the available credits based on the port grants. The packet switch routes the selected packets from ingress ports of the packet switch to the egress ports based on the port grants. In some embodiments, ingress ports generate enqueue requests based on the packets, an enqueue pipeline stage generates enqueue states based on the enqueue requests, and the request pipeline stage selects packets for routing based on the enqueue states and the available credits.