Pipeline Scheduling via Destination Register Grouping
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Solution Overview
Problem
Inter-pipeline forwarding of results in data processing systems is slower and more expensive than intra-pipeline forwarding, necessitating a reduction in inter-pipeline forwarding to enhance performance and reduce power consumption.
Innovation Solution
An apparatus with multiple processing pipelines and instruction issuing circuitry that selects pipelines based on the destination register specifier of instructions, grouping instructions with the same destination register to the same pipeline, thereby reducing inter-pipeline forwarding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are distributed across multiple processing pipelines, then processing throughput is improved, but inter-pipeline forwarding increases causing slower and more expensive operation
Solution Approach 1:
The patent segments the set of destination registers into multiple groups, with each group associated with a specific processing pipeline. This segmentation allows instructions to be routed to pipelines based on their destination register, ensuring that instructions writing to the same register are processed by the same pipeline and eliminate inter-pipeline forwarding.
Solution Approach 2:
The patent assigns different properties to different parts of the register file by creating multiple groups of destination registers, where each group is locally optimized for a specific pipeline. This local quality approach ensures that frequently forwarded data remains within the same pipeline, reducing the need for expensive inter-pipeline forwarding while maintaining high throughput.
2Productivity
If instructions are distributed across multiple processing pipelines, then processing throughput is improved, but power consumption increases due to inter-pipeline forwarding
Solution Approach 1:
The patent segments the set of destination registers into multiple groups, with each group associated with a specific processing pipeline. This segmentation allows instructions to be routed to pipelines based on their destination register, ensuring that instructions writing to the same register are processed by the same pipeline and eliminate inter-pipeline forwarding.
Solution Approach 2:
The patent assigns different properties to different parts of the register file by creating multiple groups of destination registers, where each group is locally optimized for a specific pipeline. This local quality approach ensures that frequently forwarded data remains within the same pipeline, reducing the need for expensive inter-pipeline forwarding while maintaining high throughput.
3Reliability
If instructions are kept in the same processing pipeline, then forwarding efficiency is improved, but processing throughput is reduced due to pipeline constraints
Solution Approach 1:
The patent segments the set of destination registers into multiple groups, with each group associated with a specific processing pipeline. This segmentation allows instructions to be routed to pipelines based on their destination register, ensuring that instructions writing to the same register are processed by the same pipeline and eliminate inter-pipeline forwarding.
Solution Approach 2:
The patent introduces a new dimension to pipeline organization by creating multiple pipeline groups that are independent and can operate in parallel. This dimensional change allows the system to maintain high forwarding efficiency within each pipeline while achieving high overall throughput through parallel execution across multiple pipeline groups.
Data Source
AI summary
A data processing apparatus 1 has a plurality of registers 10 of the same type of register and a plurality of processing pipelines 40, 50, each processing pipeline 40, 50 being arranged to process instructions. At least one instruction includes a destination register specifier specifying which of said registers is a destination register for storing a processing result of the at least one instruction. Instruction issuing circuitry 26 is configured to issue the at least one instruction for processing by one of the plurality of processing pipelines. The instruction issuing circuitry 26 selects the one of the plurality of processing pipelines to which the candidate instruction is issued in dependence upon the value of the destination register specifier of the candidate instruction.


