Arithmetic Processing Device Pipeline Stage Priority Control

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Solution Overview

Problem

In pipeline parallel systems, stages with longer processing times can lead to decreased throughput due to data accumulation and resource conflicts, as resources are not efficiently allocated based on actual processing times.

Innovation Solution

An arithmetic processing device measures the processing time of each pipeline stage and sets priorities in descending order, allowing for efficient resource allocation and preventing stages with longer processing times from being interrupted, thereby equalizing processing times and improving throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If pipeline parallel processing is implemented to improve throughput, then processing speed is improved, but resource conflicts and data accumulation occur when stages have unequal processing times

Engineering Contradiction:
ImprovethroughputVSAvoidprocessing efficiency stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically adjusts the priority of pipeline stages based on their actual processing times. The priority setting unit changes the execution priority of each stage according to measured performance data, making the pipeline adaptive to varying processing requirements and preventing bottlenecks caused by static priority assignments.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The measurement unit continuously monitors the processing time of each pipeline stage and feeds this information back to the priority setting unit. This feedback loop enables the system to automatically adjust priorities based on actual performance, ensuring that stages with longer processing times receive higher priority to maintain balanced throughput.

Inventive Principle:
Principle #23Feedback

2Device complexity

If resources are allocated equally to all pipeline stages, then resource allocation is simple, but stages with longer processing times cause data accumulation and reduce overall efficiency

Engineering Contradiction:
Improveresource allocation complexityVSAvoidthroughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

Instead of uniform resource allocation, the system applies differentiated priority levels to different pipeline stages based on their individual processing characteristics. Each stage receives resources proportional to its needs, with stages having longer processing times allocated higher priority, thereby optimizing overall pipeline efficiency without excessive complexity.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If pipeline stages are executed in parallel without priority differentiation, then ease of operation is maintained, but resource conflicts occur reducing processing efficiency

Engineering Contradiction:
Improvepipeline execution simplicityVSAvoidprocessing efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The pipeline system automatically determines and adjusts its own priorities based on measured processing times. The measurement unit and priority setting unit work autonomously to optimize resource allocation without requiring external intervention or complex manual configuration, maintaining ease of operation while improving processing efficiency through adaptive priority management.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11782708B2Arithmetic processing device and arithmetic processing method
Publication Date: 2023.10.10 FUJITSU LTD
  • US11782708B2 patent drawing
  • US11782708B2 patent drawing
  • US11782708B2 patent drawing

AI summary

An arithmetic processing device includes: a memory; and a processor coupled to the memory and configured to: execute a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings; measure a processing time of each of the plurality of pipeline stages; and set a priority of the plurality of pipeline stages in a descending order of the measured processing time.