Pipeline Stage Scheduling for Complex Instruction Execution

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Solution Overview

Problem

Existing data processing apparatus face challenges in efficiently executing complex instructions without increasing pipeline depth or complexity in issue stage circuitry, as dedicated execution pipelines for complex instructions can lead to longer execution times for simple instructions and increased complexity in handling complex instructions.

Innovation Solution

Implementing a data processing apparatus with a plurality of execution pipelines, where the issue circuitry schedules only the first operation of a complex instruction and delegates subsequent operation scheduling to the relevant pipeline stages, using control signals to indicate additional operations, thereby keeping pipeline depth small and avoiding increased complexity in issue stage circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a dedicated execution pipeline is provided for complex instructions, then complex instructions can be executed, but pipeline depth increases and simple instructions experience increased latency

Engineering Contradiction:
Improveability to execute complex instructionsVSAvoidpipeline depth
Core Design Contradiction:
Adaptability or versatilityVSLength of moving object

Solution Approach 1:

The execution pipeline is designed to be universal, handling both simple instructions and complex instructions through the same pipeline stages. The pipeline can execute simple operations directly and also manage complex multi-operation sequences by scheduling operations across different pipeline stages, eliminating the need for separate dedicated pipelines for complex instructions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Complex instructions are segmented into multiple individual operations that can be scheduled and executed separately across different pipeline stages. Each operation in the sequence is treated as an independent scheduling unit, allowing the pipeline to manage complex instructions through multiple smaller execution steps rather than requiring a dedicated pipeline for the entire complex operation.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If a dedicated execution pipeline is provided for complex instructions, then complex instructions can be executed, but execution time for simple instructions increases

Engineering Contradiction:
Improveability to execute complex instructionsVSAvoidexecution latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The execution pipeline is designed to be universal, handling both simple instructions and complex instructions through the same pipeline stages. The pipeline can execute simple operations directly and also manage complex multi-operation sequences by scheduling operations across different pipeline stages, eliminating the need for separate dedicated pipelines for complex instructions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The pipeline scheduling mechanism is dynamic, allowing flexible allocation of operations to pipeline stages based on the instruction type. Simple instructions can be executed immediately in available pipeline stages, while complex instructions are broken down and scheduled across multiple stages, enabling the system to adapt execution time based on instruction complexity rather than using a fixed long pipeline for all instructions.

Inventive Principle:
Principle #15Dynamics

3Ease of operation

If issue stage circuitry schedules all operations in a complex instruction sequence, then scheduling control is centralized, but issue stage circuitry complexity increases

Engineering Contradiction:
Improvescheduling controlVSAvoidissue stage circuitry complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The scheduling responsibility for subsequent operations in a complex instruction sequence is extracted from the issue stage circuitry and transferred to the execution pipeline itself. The pipeline stages are equipped with the capability to schedule their own operations based on the sequence definition, reducing the scheduling burden on the issue stage circuitry while maintaining centralized control for the first operation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The execution pipeline is designed to be self-sufficient for scheduling its own operations. Once the first operation is scheduled by the issue stage circuitry, the pipeline uses its internal resources and the sequence definition to automatically schedule subsequent operations without requiring continuous intervention from the issue stage circuitry, thereby reducing issue stage complexity.

Inventive Principle:
Principle #25Self-service

4Loss of time

If pipeline depth is reduced, then simple instructions have lower latency, but complex instruction execution becomes more difficult

Engineering Contradiction:
Improveexecution latencyVSAvoidpipeline management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

Complex instructions are segmented into multiple individual operations that can be scheduled and executed separately across different pipeline stages. Each operation in the sequence is treated as an independent scheduling unit, allowing the pipeline to manage complex instructions through multiple smaller execution steps rather than requiring a dedicated pipeline for the entire complex operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pipeline scheduling mechanism is dynamic, allowing flexible allocation of operations to pipeline stages based on the instruction type. Simple instructions can be executed immediately in available pipeline stages, while complex instructions are broken down and scheduled across multiple stages, enabling the system to adapt execution time based on instruction complexity rather than using a fixed long pipeline for all instructions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7984269B2Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instruction
Publication Date: 2011.07.19 ARM LTD
  • US7984269B2 patent drawing
  • US7984269B2 patent drawing
  • US7984269B2 patent drawing

AI summary

A data processing apparatus and method are provided for executing complex instructions. The data processing apparatus executes instructions defining operations to be performed by the data processing apparatus, those instructions including at least one complex instruction defining a sequence of operations to be performed. The data processing apparatus comprises a plurality of execution pipelines, each execution pipeline having a plurality of pipeline stages and arranged to perform at least one associated operation. Issue circuitry interfaces with the plurality of execution pipelines and is used to schedule performance of the operations defined by the instructions. For the at least one complex instruction, the issue circuitry is arranged to schedule a first operation in the sequence, and to issue control signals to one of the execution pipelines with which that first operation is associated, those control signals including an indication of each additional operation in the sequence. Then, when performance of the first operation reaches a predetermined pipeline stage in that execution pipeline, that predetermined pipeline stage is arranged to schedule a next operation in the sequence, and to issue additional control signals to a further one of the execution pipelines with which that next operation is associated in order to cause that next operation to be performed. This has been found to provide a particularly efficient mechanism for handling the execution of complex instructions without the need to provide dedicated execution pipelines for those complex instructions, and without an increase in complexity of the issue circuitry.