Pipeline Stall Handling via Thread Instruction Flushing

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Solution Overview

Problem

Processing pipelines often experience performance degradation due to frequent stalling events, such as delays in accessing data from storage, which can dominate performance, especially in systems like networking where cache misses are common.

Innovation Solution

An apparatus and method that detect stalling events by monitoring delays in accessing information and adjust the processing pipeline by flushing pending instructions from the stalled thread while retaining at least one instruction to ensure forward progress, and dynamically adjusting a threshold for triggering such actions based on the delay difference, thereby allocating resources to other threads for improved performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the processing pipeline continues to fetch and process instructions from a stalled thread, then the pipeline resources remain allocated to that thread, but the stalling event causes performance degradation and blocks other threads from utilizing available resources

Engineering Contradiction:
Improvesystem throughputVSAvoidpipeline stall duration
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts the stalled thread's instructions from the processing pipeline by flushing them, removing the harmful element (stalled instructions) that is blocking pipeline resources. This allows other threads to immediately utilize the freed resources without waiting for the stalled thread to complete, thereby improving overall system throughput while minimizing the time loss from the stall event.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If the pipeline flushes all pending instructions from a stalled thread, then resource allocation to the stalled thread is reduced, but this may waste work already done on instructions that could have completed quickly

Engineering Contradiction:
Improveoverall system performanceVSAvoidwasted instruction processing
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent applies partial action by selectively flushing only a portion of the pipeline contents related to the stalled thread rather than all instructions. The control circuitry identifies and flushes specifically the instructions associated with the stalled thread while allowing other threads' instructions to continue processing. This partial flushing approach reduces resource allocation to the stalled thread sufficiently to improve overall performance while minimizing waste of work already performed on independent instructions.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If the delay threshold for triggering stalling actions is set low, then stalling events are detected early and resources can be reallocated quickly, but this may trigger unnecessary flushes for normal delays

Engineering Contradiction:
Improveresource reallocation speedVSAvoidthreshold management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a dynamic threshold mechanism where the delay threshold is not fixed but adapts based on system conditions and historical stall patterns. The control circuitry monitors actual stall durations and adjusts the threshold accordingly, making it more sensitive during periods of frequent stalls and less sensitive during normal operation. This dynamic approach enables quick resource reallocation when genuine stalls occur while reducing false positives, thereby improving productivity without excessive unnecessary flushes.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10552160B2Handling stalling event for multiple thread pipeline, and triggering action based on information access delay
Publication Date: 2020.02.04 ARM LTD
  • US10552160B2 patent drawing
  • US10552160B2 patent drawing
  • US10552160B2 patent drawing

AI summary

A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.