Pipeline Sub-ADC Clock Phasing for Lower-Power Early Stages
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Solution Overview
Problem
The early stages of pipelined sub-ADCs in time-interleaved ADCs consume high power due to the need for high-speed amplifiers to ensure fast output settling, leading to increased power dissipation and consumption.
Innovation Solution
By using a clock signal schedule where the hold phase of a stage commences earlier than the sampling phase of the next stage, allowing more time for the amplifier output to settle, enabling the use of lower-speed amplifiers and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-speed amplifiers are used in early stages of pipelined sub-ADC to ensure fast output settling, then output settling accuracy is improved, but power consumption increases
Solution Approach 1:
The hold phase of the current stage is advanced to start before the sampling phase of the next stage begins. This preliminary action allows the amplifier output to settle during the overlap period, ensuring accurate output settling without requiring high-speed amplifiers that consume excessive power.
2Speed
If high-speed amplifiers are used in early stages of pipelined sub-ADC, then settling speed is improved, but power dissipation increases
Solution Approach 1:
By advancing the hold phase to commence before the next stage's sampling phase, the amplifier is given additional time to settle its output. This preliminary settling action eliminates the need for high-speed amplifiers, thereby reducing power dissipation while maintaining adequate settling speed.
3Use of energy by moving object
If hold phase commences earlier than next stage sampling phase, then power consumption is reduced, but timing complexity increases
Solution Approach 1:
The clock signal schedule is dynamically adjusted to create an overlapping timing window where the hold phase of the current stage commences before the sampling phase of the next stage. This dynamic timing arrangement reduces power consumption while managing timing complexity through systematic clock phase adjustment.
Data Source
AI summary
A stage of a pipelined ADC used as a sub-ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals. The first set and second set of clock signals are designed to cause the start of hold phases of the stage to occur earlier than the sample phases of the next stage. In an embodiment, the start of the hold phases is coincident with the end of an immediately preceding sample phase of the stage. As a result, more time is provided for the output of an amplifier used in the stage to settle to a final value, thus permitting use of a low speed amplifier and reduction in power consumption in the interleaved ADC. In an embodiment, the stage corresponds to an earliest stage in the pipelined sub-ADC.