High-Level Synthesis Pipeline Timing Adjustment for Execution Delay
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Solution Overview
Problem
Conventional high-level synthesis technologies face challenges in efficiently manufacturing pipeline circuits that can execute pipeline processing due to delays between consecutive processes, making it difficult to shorten the execution time of multiple processes.
Innovation Solution
An information processing device that converts first execution information into second execution information by adjusting the start timing of subsequent processing, ensuring data reads occur after data writes, based on the order of data operations in both preprocessing and main processing, thereby reducing delays and shortening the total execution time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional high-level synthesis technology is used to convert operation descriptions into HDL circuit descriptions, then the processing can be completed with standard methods, but the execution time of multiple processes cannot be shortened due to delays between consecutive processes
Solution Approach 1:
The invention performs preliminary analysis of data dependencies between processes before generating the pipeline circuit. By examining the order of data writes in the first processing and data reads in the second processing, the system determines in advance which processes can be overlapped, allowing the pipeline circuit to be configured optimally before execution without runtime delays
Solution Approach 2:
The invention dynamically adjusts the pipeline circuit configuration based on the specific data dependency relationships found in the operation description. Rather than using a fixed pipeline structure, the system adapts the pipeline stages and timing to match the actual data flow requirements, enabling efficient overlap of processes where dependencies allow
2Loss of time
If the start timing of the second processing is made earlier than the end timing of the first processing, then the total execution time is shortened, but it becomes difficult to ensure that data reads in the second processing occur after data writes in the first processing
Solution Approach 1:
The invention uses feedback from the data dependency analysis to control the pipeline timing. By continuously checking whether data read operations in the second processing occur after corresponding data write operations in the first processing, the system adjusts the pipeline stage timing to maintain correctness while maximizing overlap. This feedback mechanism ensures data dependency constraints are satisfied even with aggressive timing optimization
Solution Approach 2:
The system performs preliminary identification of all data dependency relationships between the first and second processing stages before generating the pipeline circuit. This advance analysis allows the system to pre-determine the minimum safe overlap period that guarantees data reads occur after writes, enabling timing optimization without compromising reliability
Data Source
AI summary
An information processing device includes: a memory; and a processor coupled to the memory and configured to: store first execution information that includes first processing for a plurality of data and second processing executed subsequently to the first processing; convert the first execution information into second execution information by making a start timing of the second processing earlier than an end timing of the first processing, under a restriction of an execution order in which a data read in the second processing is executed after a data write in the first processing for each of the plurality of data, on the basis of an order of data writes included in the first processing and an order of data reads included in the second processing; and output the second execution information.