Processor Pipeline Trace Storage via Store Instruction Insertion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing trace information storage methods in processors often lead to frequent buffer overflows, causing pipeline interrupts and significant performance loss due to the need for software to drain internal or external trace buffers, which are not compatible with the execution rate of the pipeline.
Innovation Solution
The solution involves using the processor pipeline to buffer trace information in a portion of memory by inserting a store instruction into specific stages of the pipeline, allowing trace data to be sent to memory using a storage instruction, thereby avoiding frequent interrupts and ensuring compatibility with the pipeline's execution rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated trace circuitry is used to capture and store trace information, then trace information can be captured during pipeline operation, but frequent buffer overflows occur causing pipeline interrupts and performance loss
Solution Approach 1:
The patent merges the trace information storage function with the existing pipeline memory structure by inserting store instructions into the pipeline. Instead of using a separate dedicated trace buffer that requires frequent draining, the trace data is stored in memory locations accessible through the pipeline's existing memory interface, combining trace capture with normal memory operations.
Solution Approach 2:
The patent makes the pipeline's memory system serve dual purposes: normal program execution and trace information storage. By using store instructions that can be inserted into the pipeline, the same memory infrastructure handles both regular data operations and trace data capture, eliminating the need for specialized trace buffer management.
2Quantity of substance
If internal or external trace buffers are used, then trace information can be accumulated, but software must frequently drain these buffers causing pipeline interrupts
Solution Approach 1:
The patent extracts the trace buffer draining operation from the pipeline execution flow by storing trace information directly in memory locations that don't require interrupt-based management. The trace data is written to memory through store instructions that execute normally within the pipeline, removing the need for separate buffer draining interrupts.
Solution Approach 2:
The patent performs trace information storage as a preliminary action within the pipeline execution flow itself. Store instructions are inserted to write trace data to memory before the pipeline needs to interrupt for buffer management, ensuring trace data is continuously available without requiring subsequent interrupt-based draining operations.
3Reliability
If trace buffers are used, then trace information can be stored, but the buffers are not compatible with the pipeline's execution rate
Solution Approach 1:
The patent makes the memory system universal by having it handle both normal program data and trace information through the same pipeline interface. The memory subsystem is already designed to operate at the pipeline's execution rate for regular operations, so using it for trace storage automatically provides compatibility without requiring specialized buffer design.
Data Source
AI summary
At least some instructions executed in a pipeline are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline. A predetermined type of store instructions flow through a subset of contiguous stages of the pipeline. A signal is received to store a portion of the trace information. A stage before the subset of contiguous stages is stalled. A store instruction of the predetermined type is inserted into a stage at the beginning of the subset of contiguous stages to enable the store instruction to reach the memory access stage at which an operand of the store instruction including the portion of the trace information is sent out of the pipeline. The store instruction is filtered from a stage of the subset of contiguous stages that occurs earlier in the pipeline than a stage in which trace information is generated.