Pipelined 2D-DCT Architecture for Low-Complexity Image Processing
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Solution Overview
Problem
The discrete cosine transform (DCT) process for image compression is computationally intensive, making it challenging to meet the requirements of low complexity and high-speed operation for System-on-Chip (SoC) type CMOS image sensors.
Innovation Solution
An image processing apparatus and method with a pipeline structure that includes an arithmetic operation unit performing discrete cosine transform using a fast AAN DCT process, optimized for hardware implementation, which reduces the number of clock cycles required for calculation and minimizes logic complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a standard separable transform scheme is applied for 2D-DCT operation, then the DCT can be performed systematically, but the computational complexity becomes too high for low-power SoC CMOS image sensors
Solution Approach 1:
The patent segments the 2D-DCT operation into multiple pipeline stages, dividing the computation into smaller sub-tasks that can be processed sequentially. Each stage handles a specific portion of the DCT calculation, breaking down the complex 80 multiplications and 464 additions into manageable steps that reduce the computational burden on each individual processing unit.
Solution Approach 2:
The patent pre-calculates and stores the scaled DCT coefficients (c0 to c7) in a lookup table before the actual DCT operation. This preliminary action allows the main processing stages to simply retrieve and use these pre-computed values, eliminating the need to perform complex trigonometric calculations during the critical DCT processing path, thereby reducing computational complexity.
2Manufacturing precision
If a standard separable transform scheme is applied for 2D-DCT operation, then complete DCT processing can be achieved, but the number of clock cycles required is too large for high-speed operation
Solution Approach 1:
The patent implements a dynamic pipeline structure where multiple data blocks can be processed in overlapping time periods. While one block is being processed in stage 1, another block can simultaneously be processed in stage 2, and so on. This dynamic parallel processing across pipeline stages significantly reduces the total clock cycles required compared to sequential processing of each complete 2D-DCT block.
Solution Approach 2:
The patent introduces a temporal dimension to the processing by organizing computations into multiple pipeline stages that operate concurrently. Instead of completing all computations for one block before starting the next, the system processes different stages of different blocks simultaneously in time, effectively adding a time dimension to the processing architecture to achieve higher throughput.
3Use of energy by stationary object
If low complexity processing is implemented, then power consumption is reduced, but processing speed may be compromised
Solution Approach 1:
The patent maintains continuous useful action through its pipeline architecture, where the arithmetic operation unit continuously processes data blocks without idle cycles. Each pipeline stage is always engaged in productive computation, eliminating wasted time and maintaining high processing throughput. This continuity allows the system to achieve high speed operation while using simple, low-power arithmetic operations in each stage.
Data Source
AI summary
An image processing apparatus and method providing a high speed pipeline structure having a low level of complexity is described. The image processing apparatus includes a memory configured to store a plurality of data in a plurality of memory locations, where an ordinally specified data is in a corresponding ordinal memory location.