Pipelined ADC Digital Correction Without Adders
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Solution Overview
Problem
Conventional digital correction circuits for pipelined analog-to-digital converters (ADCs) require a long operation time due to the involvement of a large number of gate stages in shift-and-add operations.
Innovation Solution
A digital correction circuit with N stages of second sub-circuits, utilizing NAND gates, NOR gates, and D-type flip-flops, which synchronizes digital codes without the need for adders, optimizing operation time by distributing operations across multiple stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional adders are used to perform shift-and-add operations in the digital correction circuit, then the circuit can correctly eliminate redundancy codes, but the operation time becomes excessively long due to the large number of gate stages required
Solution Approach 1:
The patent extracts and removes the adder components from the digital correction circuit. Instead of using conventional adders to perform shift-and-add operations, the invention uses a simplified logic circuit that directly processes the 2-bit codes from multiple stages. This extraction of the adder component eliminates the time-consuming gate stages while maintaining the ability to correctly eliminate redundancy codes and produce accurate quantized bits.
Solution Approach 2:
The patent replaces the mechanical/additive system (adders performing shift-and-add operations) with a logical system (logic gates directly computing quantized bits). Instead of mechanically adding binary numbers through multiple gate stages, the invention uses logical operations to directly determine the quantized bit values, significantly reducing operation time while preserving correction accuracy.
2Reliability
If a large number of gate stages are used in the shift-and-add circuit, then the circuit can perform complete redundancy elimination, but the circuit complexity and operation time increase significantly
Solution Approach 1:
The patent extracts the essential function of redundancy elimination from the complex shift-and-add circuitry. By removing the adders and their associated gate stages, the invention retains only the necessary logic to identify and eliminate redundancy codes, thereby reducing circuit complexity while maintaining complete redundancy elimination capability.
Solution Approach 2:
The patent segments the correction process into independent stage-wise operations. Each stage processes its 2-bit code independently through simplified logic, rather than requiring a monolithic shift-and-add operation across all stages. This segmentation reduces overall circuit complexity while ensuring complete redundancy elimination through systematic processing of each stage's contribution.
3Measurement precision
If conventional shift-and-add operations are used to process codes from N stages, then all quantized bits can be obtained, but the operation time becomes unacceptably long
Solution Approach 1:
The patent replaces the mechanical shift-and-add operation sequence with parallel logical computations. Instead of sequentially shifting and adding codes from N stages through multiple gate stages, the invention uses logical operations that can determine quantized bit values more directly, significantly improving operation speed while maintaining quantized bit accuracy.
Solution Approach 2:
The patent performs preliminary processing of each stage's 2-bit code before combining them. By pre-processing the codes from N stages through simplified logic gates that prepare the data in advance, the circuit avoids time-consuming sequential operations and can quickly produce accurate quantized bits, thereby improving productivity without sacrificing precision.
Data Source
AI summary
A digital correction circuit for a pipelined analog-to-digital converter (ADC) is disclosed. Compared to the conventional digital correction circuit which uses adders to perform operations in ADC digital correction part and hence needs a rather long operation time, the digital correction circuit of this invention can reduce the time needed in operations in the finial digital correction circuits and thus can optimize operation time, by allocating the operations to a plurality of pipeline stages of second sub-circuits configured to synchronize digital codes, each of which can perform part of the operations only with NAND gates, NOR gates, phase inverters and D-type flip-flops, without needing to use adders.