Pipelined ADC Calibration Using Correlated Capacitive Dither
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Solution Overview
Problem
Existing calibration techniques for pipelined ADCs consume a significant portion of the dynamic range and power due to the use of uncorrelated dither signals, which is undesirable in nanometer CMOS processes where dynamic range is limited.
Innovation Solution
A pipelined ADC design that injects a random signal using a random sequence digital-to-analog converter (RSDAC) with multiple capacitive branches in parallel, allowing for accurate calibration and error correction without sacrificing output accuracy, by trimming and cycling injection capacitors to reduce power and dynamic range consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If uncorrelated dither signals are used for calibration in pipelined ADCs, then calibration accuracy is improved, but power consumption and dynamic range usage increase significantly
Solution Approach 1:
The patent changes the correlation parameter of the calibration signal from uncorrelated (traditional dither) to correlated (pseudo-random sequence with known pattern). This allows the calibration signal to be correlated out at the digital output, maintaining calibration accuracy while reducing the power and dynamic range requirements for signal injection.
Solution Approach 2:
The patent uses a digital copy of the pseudo-random sequence at the output stage to correlate and remove the calibration signal. Instead of using a large analog dither signal, a digital correlation operation replicates the calibration process virtually, reducing hardware power consumption while maintaining calibration effectiveness.
2Measurement precision
If uncorrelated dither signals are used for calibration in pipelined ADCs, then calibration accuracy is improved, but dynamic range consumption increases
Solution Approach 1:
The patent changes the signal correlation parameter from uncorrelated to correlated, enabling the calibration signal to be identified and removed through digital correlation. This reduces the dynamic range required for calibration signal injection, leaving more dynamic range available for the actual analog input signal.
3Measurement precision
If calibration signals are injected into quantizer, then gain errors are corrected, but errors may be magnified through subsequent stages
Solution Approach 1:
The patent implements a feedback mechanism where the digital output is correlated with the injected pseudo-random sequence to extract calibration information. This closed-loop approach ensures that gain errors are corrected at the quantizer stage without propagating amplified errors to subsequent stages, as the calibration signal is removed before further processing.
Data Source
AI summary
A device and method for correlation-based background calibration of pipelined converters with a reduced power penalty. A pipelined analog-to-digital converter (ADC) utilizes a random or pseudorandom signal to reduce the quantization error of subconverting stages. Stages within the ADC comprise an injection circuit having a plurality of capacitive branches in parallel. Less than all of the branches can function during a given clock cycle of the ADC. This allows a subconverting stage within the ADC to be accurately trimmed before operation using a large amplitude signal. At the same time, the capability to inject smaller amplitude random or pseudorandom signals into the subconverting stage during operation is maintained, saving valuable dynamic range and power. The various capacitive branches are cycled through either randomly or in sequence such that the quantizer manifests the same average gain error over time for which the quantizer was initially trimmed.