Pipelined ADC Channel Interleaving for Faster Residual Quantization
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Solution Overview
Problem
High-precision high-speed pipelined ADCs are limited by the total time of the sampling and amplification phases, and the quantization time of sub-ADCs, which restrict their speed and require significant cost increases to improve performance.
Innovation Solution
Analog-to-digital conversion method with staggered sampling and amplification phases, and time-interleaved stage-2 sub-ADCs, allowing each channel to have a complete clock cycle for sampling and quantization, reducing the need for high-speed operation and minimizing the requirements of the inter-stage gain amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the pipelined ADC operates at high speed, then the conversion rate is improved, but the total time required for sampling and amplification phases becomes insufficient, limiting the speed
Solution Approach 1:
The patent divides the ADC operation into two independent channels: a first channel dedicated to sampling and quantization, and a second channel dedicated to amplification. This segmentation allows both operations to proceed simultaneously in different channels, effectively doubling the throughput and resolving the time constraint on single-channel operation.
Solution Approach 2:
While the first channel is performing sampling and quantization during its clock cycle, the second channel simultaneously performs amplification of previously sampled signals. This continuous parallel operation ensures that no time is wasted waiting for sequential completion, maintaining continuous useful action across both channels.
2Speed
If the inter-stage gain amplifier operates at high speed with high gain, then the amplification is improved, but the gain bandwidth and slew rate requirements increase significantly
Solution Approach 1:
The patent performs sampling and quantization in the first channel before the signal is passed to the second channel for amplification. This preliminary action in the first channel prepares the signal in advance, allowing the second channel's amplifier to operate at a more relaxed speed with lower gain bandwidth and slew rate requirements, while still achieving high overall conversion speed through parallel channel operation.
3Productivity
If multiple sub-ADCs are used in parallel, then the conversion speed is improved, but mismatch issues arise between channels
Solution Approach 1:
The patent segments the functionality between two channels such that the first channel performs sampling and quantization while the second channel performs amplification. This functional segmentation reduces interaction between channels and minimizes mismatch issues compared to traditional parallel sub-ADC architectures where multiple ADCs must be tightly matched.
Data Source
AI summary
The present disclosure provides an analog-to-digital conversion method applied to an analog-to-digital converter and including: for any clock cycle, amplifying, through an inter-stage gain amplifier, a first residual stored in a sampling capacitor corresponding to a first analog-to-digital conversion channel, and sampling the amplified first residual through a stage-2 sub-analog-to-digital converter corresponding to the first analog-to-digital conversion channel; sampling and quantizing an analog signal through a stage-1 sub-analog-to-digital converter, and storing an obtained second residual in a sampling capacitor corresponding to a second analog-to-digital conversion channel; and generating a digital signal according to output signals of the stage-1 and stage-2 sub-analog-to-digital converters; and for any two adjacent clock cycles, an analog-to-digital conversion channel serving as the second analog-to-digital conversion channel in a current clock cycle serves as the first analog-to-digital conversion channel in a next clock cycle. The present disclosure further provides an analog-to-digital converter and a base station.