Pipelined ADC Calibration Using Multi-Level Dither Correlation
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Solution Overview
Problem
Pipelined analog-to-digital converters (ADCs) face limitations due to inter-stage gain errors and non-linearity, which are exacerbated by the need for high-resolution back-end pipelines to accurately calibrate dither signals, leading to power consumption and accuracy issues.
Innovation Solution
Injecting a small, multi-level digital dither signal with an odd number of levels and proper fractional amplitude into stages near the input, and optionally using an additional large dither to reduce non-linearity effects in back-end stages, allowing for calibration and correction of gain errors without requiring excessive hardware or accuracy in the back-end pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a small dither signal is used to conserve dynamic range, then power consumption and dynamic range overhead are reduced, but the back-end pipeline requires higher accuracy to maintain calibration precision
Solution Approach 1:
The patent changes the parameters of the dither signal from conventional small-amplitude to large-amplitude multi-level signal with odd number of levels. This parameter change allows the dither to occupy more quantization levels in the back-end pipeline, improving calibration accuracy without requiring increased back-end resolution. The large amplitude ensures the dither signal is sufficiently strong relative to quantization noise while the multi-level structure maximizes information content.
Solution Approach 2:
The patent transitions from conventional two-level dither to multi-level dither with odd number of levels. This dimensional expansion in signal space allows the dither to better probe the non-linearity of back-end stages. The odd number of levels provides symmetric distribution around zero, improving correlation-based error detection accuracy without requiring higher back-end bit resolution.
2Measurement precision
If the back-end pipeline accuracy is increased to improve dither signal digitization, then calibration accuracy improves, but power consumption and hardware complexity increase
Solution Approach 1:
Instead of changing the back-end pipeline accuracy, the patent changes the dither signal parameters (amplitude and number of levels). By using large-amplitude multi-level dither with odd number of levels, the signal充分利用 the existing back-end quantization levels, achieving high calibration accuracy without modifying the back-end hardware resolution or complexity.
Solution Approach 2:
The patent applies excessive action by using a large-amplitude dither signal that deliberately exceeds the conventional small dither approach. This large-amplitude signal ensures sufficient signal-to-quantization-noise ratio in the back-end pipeline, allowing accurate calibration even with fixed back-end resolution, thereby avoiding the need to increase back-end hardware accuracy.
3Ease of manufacture
If conventional two-level dither is used, then implementation is simple, but calibration accuracy is limited by back-end resolution and quantization noise
Solution Approach 1:
The patent extends the dither signal from two levels to multiple levels (odd number). This dimensional expansion in signal space provides richer information for correlation-based error detection. The multi-level structure better probes the transfer function non-linearity of ADC stages, improving calibration precision while maintaining practical implementability through lookup table generation.
Solution Approach 2:
The patent changes the dither signal parameters from two-level to multi-level with odd number of levels and increases the amplitude. These parameter changes enhance the dither's ability to overcome quantization noise in the back-end pipeline, improving calibration precision without significantly complicating the generation process through pre-computed lookup tables.
4Measurement precision
If dither amplitude is increased to overcome quantization noise, then calibration accuracy improves, but dynamic range consumption increases
Solution Approach 1:
The patent uses multi-level dither with odd number of levels, which distributes the signal energy more efficiently across the dynamic range. This dimensional change allows the dither to achieve high calibration accuracy without requiring excessive amplitude, as the multi-level structure provides better signal-to-noise ratio through improved correlation detection capability.
Solution Approach 2:
The patent optimizes the dither amplitude parameter to be large enough to overcome quantization noise but not excessively large. The multi-level structure with odd number of levels allows this optimized amplitude to achieve maximum calibration accuracy while minimizing dynamic range consumption, as each level contributes efficiently to the correlation-based error detection.
Data Source
AI summary
A method and a corresponding device for calibrating a pipelined analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into one of a flash component and a multiplying digital-to-analog converter (MDAC) in at least one stage in the ADC. For each stage of the at least one stage a correlation procedure is performed to estimate, based on an output of the ADC, an amount of gain experienced by the injected dither after propagating through the stage. The stage is then calibrated based on its respective gain estimate.