Pipelined ADC Double Sampling for Relaxed Residue Amplifier Settling
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Solution Overview
Problem
Pipelined analog to digital converters face challenges in meeting residue amplifier gain-bandwidth requirements, leading to complex timing issues and increased power consumption.
Innovation Solution
The implementation of a time-interleaved, double sampling scheme with two sets of sampling and feedback capacitors, allowing for a full clock cycle for residue amplifier settling and reducing gain-bandwidth requirements, while also sharing a single residue amplifier between two pipeline stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single sampling capacitor and feedback capacitor are used with sequential sampling and resolving operations, then the circuit complexity is reduced, but the residue amplifier gain-bandwidth requirements increase and timing problems become difficult to meet
Solution Approach 1:
The patent divides the capacitor system into two separate sets: a first set (C1n-C4n, C1p-C4p) for sampling and a second set (C5n-C8n, C5p-C8p) for resolving. This segmentation allows simultaneous operation of sampling and resolving phases, eliminating the sequential bottleneck and reducing gain-bandwidth requirements while maintaining manageable circuit complexity through modular organization.
Solution Approach 2:
The patent transitions from a single-clock-phase sequential operation to a two-dimensional time-interleaved operation using two clock phases (Φ1 and Φ2). During Φ1, the first capacitor set samples while the second set resolves; during Φ2, the roles reverse. This dimensional expansion in time management resolves the timing conflicts and relaxes amplifier bandwidth requirements.
2Speed
If sequential sampling and residue calculation are performed within a single clock cycle, then the clock frequency can be reduced, but the time budget for residue resolution is limited and amplifier bandwidth requirements increase
Solution Approach 1:
The patent implements continuous useful action by overlapping the sampling phase of one capacitor set with the resolving phase of the other set. While the first set samples during Φ1, the second set simultaneously resolves its residue during the same period. This continuous parallel operation effectively doubles the residue resolution time budget without increasing clock frequency, directly addressing the time-bandwidth tradeoff.
3Manufacturing precision
If more time is allocated for residue amplification, then gain-bandwidth requirements are reduced, but the throughput of the converter decreases
Solution Approach 1:
The patent employs periodic action through two distinct clock phases (Φ1 and Φ2) that alternately assign sampling and resolving functions to the two capacitor sets. During Φ1, set 1 samples and set 2 resolves; during Φ2, set 1 resolves and set 2 samples. This periodic switching ensures that residue amplification always has a full clock period while maintaining continuous throughput by keeping both sets actively processing different samples simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases throughput, reduces power consumption, and relaxes the gain-bandwidth requirements of residue amplifiers, enabling more efficient electronic signal conversion.
Implementation Method 1
a sampling capacitor charged on one phase of a clock... The sampling capacitor stores the analog to digital converter input minus the coarse digital to analog converter output
Implementation Method 2
a corresponding feedback capacitor that is charged on the opposite phase of the clock... During this phase (i.e., Φ2), the residue is calculated as the difference between Vin and the MDAC output
Data Source
AI summary
Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period.