Pipelined ADC With Dynamic Reference and 2-Stage Sample-and-Hold
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Solution Overview
Problem
Current analog-to-digital converters (ADCs) face challenges in achieving high-speed operation at sampling rates of several tens of GS/s while maintaining low power consumption, which is essential for supporting high-speed backplane communication links of 10-20 Gbps, due to limitations in existing linear equalizers and high power consumption in existing ADC designs.
Innovation Solution
A low-power pipelined ADC is proposed, utilizing a 2-stage sample-and-hold (S/H) mechanism to double conversion time and a digital-analog converter (DAC) to limit frequency bandwidth, along with a reference voltage generator that uses a resistive ladder and multiplexing to reduce parasitic capacitance and correct non-linearity, enabling efficient high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a converter operates at a sampling rate of several tens of GS/s, then high-speed communication capability is improved, but power consumption increases excessively
Solution Approach 1:
The ADC is divided into multiple pipeline stages, each handling a portion of the conversion process. This segmentation allows each stage to operate at lower individual speeds while achieving high overall sampling rates through parallel processing, thereby reducing power consumption per stage while maintaining high-speed capability.
Solution Approach 2:
The patent employs periodic sampling and holding operations where the sample-and-hold circuit captures signals periodically at optimized intervals. This periodic action allows the system to process high-speed signals while keeping circuits in low-power states between sampling events, reducing overall power consumption.
2Measurement precision
If a converter achieves high resolution of 6 bits or more, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The high-resolution conversion process is segmented into multiple pipeline stages, where each stage contributes a portion of the final resolution. This divides the complex 6-bit or higher resolution task into simpler sub-tasks that can be performed by less complex individual circuits, reducing overall device complexity while achieving high measurement precision.
Solution Approach 2:
The patent uses dynamic element matching and switching techniques where circuit elements are dynamically configured based on the conversion stage and required precision. This allows the system to achieve high resolution only when needed during the conversion process, reducing average complexity compared to always using maximum precision circuits.
3Ease of operation
If a linear equalizer using current summer is used, then ease of operation is improved, but speed performance deteriorates due to conventional limits
Solution Approach 1:
The patent replaces the analog current summer mechanism with a digital equalization approach. Digital circuits substitute for the analog current manipulation, enabling high-speed operation while maintaining the ease of equalization through programmable digital algorithms rather than fixed analog circuitry.
Solution Approach 2:
The equalizer transitions from a static analog current summer to a dynamic digital system that can be reconfigured through software. This allows the equalization parameters to be dynamically adjusted for different signal conditions while operating at high speeds, combining ease of operation with high-speed performance.
Data Source
AI summary
Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.