Pipelined ADC Sampling Layout for High Throughput With Lower Power
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Solution Overview
Problem
Pipelined analog-to-digital converters face challenges in achieving high sample rates with low power consumption while avoiding frequency response issues and spatial inefficiencies due to parallel signal processing, which often require additional circuitry and power consumption to correct for mismatches and timing inaccuracies.
Innovation Solution
A pipelined ADC design where the first stage samples the input signal at the full sample rate, and subsequent stages operate at reduced frequencies using parallel sampling circuitry, avoiding concurrent sampling and utilizing shared amplifier and reference voltages to reduce power consumption and spatial requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel pipeline channels are used to achieve high throughput, then sample rate is improved, but power consumption and circuit area increase due to multiple concurrent sampling circuits
Solution Approach 1:
The patent applies periodic action by having subsequent pipeline stages sample the signal at reduced frequencies (e.g., one-half the sample frequency for two parallel pipelines) rather than at the full sample rate. This allows the ADC to achieve high throughput through parallel processing while reducing power consumption by having stages operate periodically at lower frequencies, with only the first stage operating at full sample rate.
2Productivity
If parallel pipeline channels sample on multiple clock edges to increase throughput, then sample rate is improved, but frequency response spurs are generated due to mismatches and timing inaccuracies
Solution Approach 1:
The patent segments the parallel pipeline channels to sample the input signal at different times rather than concurrently. The first pipeline stage samples on one clock edge, while subsequent stages sample at reduced frequencies, ensuring all stages ultimately sample on the same clock edge. This segmentation approach maintains high throughput while eliminating the frequency response spurs caused by concurrent sampling mismatches.
3Measurement precision
If additional circuitry is added to correct for channel mismatches and timing inaccuracies, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies preliminary action by designing the sampling circuitry to inherently sample on the same clock edge from the outset, rather than requiring corrective circuitry to fix timing mismatches after the fact. The first stage samples on one clock edge, and subsequent stages are designed to sample at reduced frequencies that align with the same clock edge, eliminating the need for additional calibration and auto-zeroing circuitry.
Data Source
AI summary
A pipelined analog-to-digital converter is provided that has advantages of both a high input sample rate as well as low power consumption due to having all but the first pipeline stage operate at a frequency that is a fraction of the input sample rate. The first stage of the pipelined ADC has an internal operating frequency that is the full ADC sample rate, and samples the input signal on the same clock edge for each sample. Subsequent pipeline stages have parallel input sampling circuitry that samples provided input signals at a reduced rate. Since the input sampling circuitry operates at a reduced frequency, power consumption is reduced by those stages. Further, by virtue of sampling the input signal on the same clock edge for each sample, frequency response image generation issues associated with ADC architectures that sample the input signal on more than one clock edge are avoided.