Pipelined ADC Metastability Detection With Auxiliary Comparator Path

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Solution Overview

Problem

Pipelined analog-to-digital converters (ADCs) suffer from metastability issues due to flash ADC comparators not having sufficient time to regenerate input voltage levels, leading to bit error rate (BER) degradation, which affects signal-to-noise ratio (SNR) in applications like wireless communication and radars.

Innovation Solution

Implementing an auxiliary path in the pipelined ADC that includes metastability comparators to detect and provide additional time for flash ADC comparators to settle, allowing residues to be processed through this path if metastability is detected, thereby reducing BER.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the flash ADC comparator is designed to operate at high speed, then the conversion speed is improved, but the comparator does not have sufficient time to regenerate input voltage levels, leading to metastability and bit error rate degradation

Engineering Contradiction:
Improveconversion speedVSAvoidbit error rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent divides the ADC system into two separate paths: a main path for normal high-speed operation and an auxiliary path for metastability correction. The auxiliary path includes additional comparators that specifically detect and correct metastability errors, allowing the main path to operate at high speed without compromising reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces metastability comparators as intermediary components that monitor the output of the flash ADC comparators. These metastability comparators detect uncertain states and trigger corrections, acting as a mediator between the high-speed flash ADC and the final output to ensure reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the comparator is given more time to settle, then the bit error rate is reduced, but the conversion speed decreases

Engineering Contradiction:
Improvebit error rateVSAvoidconversion speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements a dynamic system where the comparison process can extend into the auxiliary path if metastability is detected. The system adapts its operation time based on the input signal characteristics, allowing fast conversion for stable signals and extended processing only when necessary to correct metastability errors.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The metastability comparators perform preliminary detection of potential errors before the final output is generated. By detecting metastability conditions early in the process, the system can trigger corrections in the auxiliary path before the error affects the final result, maintaining both speed and reliability.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If an auxiliary path is added to detect and correct metastability, then the bit error rate is significantly reduced, but the device complexity increases

Engineering Contradiction:
Improvebit error rateVSAvoidconverter structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the auxiliary metastability detection path with the main conversion path by sharing common components such as the flash ADC comparators and input signals. The auxiliary path uses the same comparator outputs and only adds detection logic, avoiding complete duplication and reducing overall complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The auxiliary path is designed to be self-activating based on metastability detection. When the metastability comparators detect an uncertain state, they automatically trigger the correction process without requiring external control logic, reducing the complexity of control circuits while maintaining reliability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20260081613A1Metastability error detection and BER improvement technique in pipelined adcs
Publication Date: 2026.03.19 TEXAS INSTRUMENTS INC
  • US20260081613A1 patent drawing
  • US20260081613A1 patent drawing
  • US20260081613A1 patent drawing

AI summary

In an example, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to an output of the flash ADC, and a first amplifier having an input coupled to an output of the DAC and the sampling switch. The main path includes a second stage coupled to the first stage and an input of a second amplifier. The main path also includes a backend ADC having an input coupled to an output of the second amplifier. The auxiliary path includes a plurality of metastability comparators coupled to the flash ADC.