Pipelined ADC MSB Sampling for Faster Bit Conversion
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Solution Overview
Problem
Pipelined analog-to-digital converters (ADCs) face inefficiencies in determining the most-significant bit (MSB) during the sampling process, leading to increased processing time and power consumption, especially in high-resolution applications.
Innovation Solution
Configuring at least one sub-ADC in the pipeline to determine the MSB while the input signal is being sampled, reducing the need for additional comparators and allowing simultaneous bit conversion operations across stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the MSB determination is performed after sampling in conventional pipelined ADCs, then the conversion process is completed sequentially, but the processing time and power consumption increase
Solution Approach 1:
The patent applies preliminary action by determining the MSB during the sampling phase before the main conversion process completes. The sub-ADC determines the MSB of the input signal while the sampler is still sampling, allowing the MSB to be ready before other bit conversion operations finish. This overlaps operations to reduce total processing time and increase throughput.
2Productivity
If additional comparators are used to determine MSB during sampling, then bit conversion can occur simultaneously across stages, but the device complexity increases
Solution Approach 1:
The patent applies universality by making the sub-ADC perform multiple functions: it converts the input signal to digital bits like other sub-ADCs, and simultaneously determines the MSB during the sampling phase. This multi-functionality allows MSB determination without adding dedicated comparator circuits, maintaining device complexity while enabling simultaneous bit conversion operations across stages.
3Use of energy by stationary object
If MSB determination is delayed until sampling completes, then the conversion process is simpler to manage, but power consumption increases due to sequential processing
Solution Approach 1:
The patent applies continuity of useful action by overlapping the MSB determination process with the sampling operation. Instead of waiting for sampling to complete before determining the MSB, the sub-ADC continuously performs both sampling and MSB determination in parallel. This eliminates idle time and reduces the overall operational duration, thereby reducing power consumption despite the increased operational complexity.
Data Source
AI summary
An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.