Pipelined ADC Architecture Using Pre-Estimated Bits for Speed and Resolution
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Solution Overview
Problem
Pipelined analog-to-digital converters face limitations in achieving high-speed and high-resolution conversions due to low resolution, complex multi-stage architectures, and power consumption issues, with trade-offs between speed and resolution.
Innovation Solution
A sub-range SAR ADC assisted pipelined ADC architecture, where pre-estimated bits are generated by the first sub-range ADC to allow the MDAC and subsequent SAR ADCs to process the next sample simultaneously, utilizing flash comparators for rapid control bit generation and successive approximation for error calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a pipelined ADC architecture is used to achieve high-speed conversion, then conversion speed is improved, but resolution deteriorates
Solution Approach 1:
The ADC is divided into multiple stages: a first sub-range ADC that generates pre-estimated bits during the MDAC multiplication phase, and a second sub-range ADC that refines the conversion. This segmentation allows parallel processing where the first stage works on coarse estimation while the MDAC processes, and the second stage performs fine refinement, thereby achieving both high speed and high resolution without requiring a complex multi-stage pipeline architecture.
2Measurement precision
If a multi-stage architecture is adopted to improve resolution, then resolution is improved, but device complexity increases
Solution Approach 1:
The first sub-range ADC performs preliminary estimation of the digital bits during the time when the MDAC is performing multiplication. This preliminary action generates pre-estimated bits that are then used by the second sub-range ADC to perform the final high-resolution conversion. By performing the coarse estimation in advance during overlapping time, the need for complex multi-stage sequential processing is reduced, simplifying the overall architecture while maintaining high resolution.
3Measurement precision
If significant bit redundancy calibration is performed to satisfy high-resolution requirements, then resolution is improved, but power consumption increases
Solution Approach 1:
The invention extracts the calibration function from a separate power-consuming calibration circuit and integrates it into the second sub-range ADC's successive approximation process. The pre-estimated bits from the first sub-range ADC are used directly as starting points for the second stage's calibration, eliminating the need for redundant calibration circuits and reducing overall power consumption while maintaining high resolution through the combined estimation-refinement approach.
Data Source
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AI summary
A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input