1-Bit Pipelined ADC Cell Circuit for Constant Reference Loading
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Solution Overview
Problem
Pipelined ADCs face challenges in reducing power consumption and eliminating the need for full settling of voltage on sampling capacitors, which is necessary due to varying charge delivery from a voltage reference dependent on the input signal, leading to increased power consumption and longer sampling times for high-speed operations.
Innovation Solution
A signal-independent voltage reference loading circuit is introduced, where capacitors are connected to a common mode reference ground during sampling phases and to reference contacts during charge transfer phases, allowing for constant charge delivery independent of the input signal, reducing the reliance on full settling and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a voltage reference is used to deliver charge to sampling capacitors in a pipelined ADC, then the ADC can perform conversion operations, but the charge delivery varies with input signal causing increased power consumption and requiring full settling
Solution Approach 1:
The patent extracts the signal-dependent charge delivery problem from the voltage reference and relocates it to a dedicated dump circuit. The voltage reference is decoupled from direct connection to sampling capacitors, and only provides charge during specific phases through controlled switches, separating the reference function from the variable charge delivery function.
Solution Approach 2:
The patent introduces a dump circuit as an intermediary between the voltage reference and the sampling capacitors. This dump circuit acts as a buffer that absorbs excess charge and regulates the charge delivery, preventing direct signal-dependent loading on the voltage reference and reducing power consumption requirements.
2Productivity
If charge delivery from voltage reference varies with input signal, then conversion can be performed, but full settling of voltage on sampling capacitors is required
Solution Approach 1:
The patent performs preliminary charge delivery to the sampling capacitors during a dedicated phase before the conversion operation. By pre-charging the capacitors in advance through controlled switches and the dump circuit, the system eliminates the need for time-consuming settling periods during the critical conversion phase, thus improving productivity without sacrificing accuracy.
3Quantity of substance
If voltage reference is continuously connected to sampling capacitors, then charge can be delivered, but power consumption increases and linearity degrades
Solution Approach 1:
The patent implements periodic connection of the voltage reference to the sampling capacitors through clocked switches that enable charge transfer only during specific phases of the conversion cycle. This periodic action allows the voltage reference to be disconnected during other phases, significantly reducing average power consumption while maintaining sufficient charge delivery for conversion operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces power consumption, maintains high-speed operation without full settling, and enables the construction of a 4x interleaved pipelined ADC by ensuring constant charge delivery from the reference buffer, improving linearity and data rate.
Implementation Method 1
a first capacitor, having a first plate and a second plate, and a second capacitor, having a third plate and a fourth plate
Implementation Method 2
a differential amplifier, having a positive input end, a negative input end, a positive output end and a negative output end, for outputting a residue output signal
Data Source
AI summary
The present invention discloses a 1-bit cell circuit used in a pipelined analog to digital converter. The 1-bit cell circuit comprises a reference buffer for providing a reference voltage; a sample and charge transfer circuit for receiving an input signal to generate an output signal; and a dump circuit for dumping said reference voltage; wherein said reference buffer selectively connects to one of said sample and charge transfer circuit and said dump circuit according to said input signal.