Pipelined ADC Using Single Residue Amplifier for Low-Power Speed

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Solution Overview

Problem

Existing analog-to-digital converters, such as flash-type and sigma delta converters, face challenges in power consumption and implementation area, while SAR-type converters have low operation speed, and as the number of converters increases in electronic devices, power consumption and area usage become significant issues.

Innovation Solution

A pipelined analog-to-digital converter with a first stage circuit generating M higher bits and a second stage circuit sequentially amplifying a residue voltage and comparison voltage using a single residue amplifier for N lower bits, reducing power consumption and enhancing accuracy through binary search conversion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a flash-type analog-to-digital converter is used, then operation speed is improved, but power consumption and implementation area increase

Engineering Contradiction:

Improveoperation speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The converter is divided into multiple stages: a first stage circuit that processes higher bits and a second stage circuit that processes lower bits. This segmentation allows each stage to operate independently with fewer resources, reducing overall power consumption while maintaining high operation speed through parallel processing capabilities.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from a single-stage high-speed converter to a multi-stage pipelined architecture, adding the time dimension through sequential processing stages. This allows the system to achieve high speed in each stage while distributing power consumption across multiple stages, effectively resolving the contradiction between speed and power consumption.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If a flash-type analog-to-digital converter is used, then operation speed is improved, but implementation area increases

Engineering Contradiction:

Improveoperation speedVSAvoidimplementation area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The implementation area is segmented into multiple stages, with each stage requiring fewer comparators and less area. The first stage handles higher bits with reduced complexity, and the second stage handles lower bits, thereby reducing the total implementation area compared to a single-stage flash converter while maintaining high operation speed.

Inventive Principle:

Principle #1Segmentation

3Use of energy by moving object

If a SAR-type analog-to-digital converter is used, then power consumption and implementation area are reduced, but operation speed decreases

Engineering Contradiction:

Improvepower consumptionVSAvoidoperation speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The invention merges the advantages of SAR-type converters (low power consumption, small area) with high-speed processing capabilities by implementing a pipelined architecture. The multiple stages process different bit groups in parallel, achieving both low power consumption and high operation speed simultaneously.

Inventive Principle:

Principle #5Merging (Combining)

4Adaptability or versatility

If multiple analog-to-digital converters are used in electronic devices, then conversion capability is improved, but power consumption and area usage increase

Engineering Contradiction:

Improveconversion capabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The pipelined analog-to-digital converter is designed with multi-functionality to handle different conversion requirements within a single integrated circuit. The modular stage-based architecture allows the same hardware to perform multiple conversion tasks, reducing the need for multiple separate converters and thereby lowering overall power consumption and area usage.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250219651A1Pipelined analog-to-digital converter and method of analog-to-digital conversion

Publication Date: 2025.07.03 SAMSUNG ELECTRONICS CO LTD

AI summary

A pipelined analog-to-digital converter includes a first stage circuit and a second stage circuit. The first stage circuit performs an analog-to-digital conversion on an analog input voltage to generate a first output signal including M higher bits among (M+N) bits of a digital output code corresponding to the analog input voltage, and generates a residue voltage corresponding to N lower bits among the (M+N) bits of the digital output code wherein M and N are natural numbers. The second stage circuit includes a residue amplifier configured to sequentially amplifying the residue voltage and a comparison voltage to generate an amplified residue voltage and an amplified comparison voltage.