Pipelined ADC Architecture Using Sub-Range SAR Pre-Estimation
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Solution Overview
Problem
Pipelined analog-to-digital converters (ADCs) face challenges in achieving high-speed and high-resolution conversions due to limited closed-loop bandwidth and systemic redundancy errors, leading to complex designs and increased power consumption.
Innovation Solution
A sub-range ADC assisted pipelined ADC architecture, utilizing sub-range SAR ADCs to pre-estimate bits and reduce the burden on the MDAC, allowing for faster conversion without compromising resolution by using flash comparators and successive approximation to generate control and digital bits efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multi-stage architecture is adopted to achieve high resolution, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the ADC into two functional segments: an MDAC stage that performs multiplication and coarse conversion, and a sub-range ADC stage that handles fine conversion. This segmentation allows each stage to be optimized independently, achieving high resolution without requiring a complex multi-stage architecture. The MDAC handles the most significant bits while the sub-range ADC refines the least significant bits, resolving the contradiction between resolution and complexity.
2Measurement precision
If the bit number of the MDAC is increased to improve resolution, then measurement precision is improved, but closed-loop bandwidth is reduced
Solution Approach 1:
The conversion process is segmented into two parallel paths: the MDAC path that operates at high speed with limited bits, and the sub-range ADC path that operates at lower speed but provides high resolution. By segmenting the resolution requirements between these two paths, the system achieves high overall resolution without forcing the MDAC to handle excessive bit numbers that would reduce its closed-loop bandwidth.
Solution Approach 2:
The MDAC performs preliminary multiplication and generates control bits in advance, which are then used by the sub-range ADC to guide its fine conversion process. This preliminary action allows the sub-range ADC to focus only on refining the least significant bits, thereby achieving high resolution without requiring the MDAC to process all bits at high speed, preserving the MDAC's closed-loop bandwidth.
3Use of energy by moving object
If a SAR ADC is used to improve power efficiency, then use of energy is improved, but conversion speed is reduced
Solution Approach 1:
The patent applies different ADC architectures to different parts of the conversion process based on their local requirements: the MDAC uses a high-speed architecture optimized for the multiplication and coarse conversion phase, while the sub-range ADC uses a power-efficient SAR architecture optimized for the fine conversion phase. This local quality approach allows each component to operate at optimal efficiency for its specific function, resolving the contradiction between power consumption and conversion speed.
Data Source
AI summary
A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input.