Pipelined ADC Stage Sharing for Lower Area and Power
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Solution Overview
Problem
Pipelined ADCs face increased power consumption and layout area in high-speed applications due to the need for larger components and higher power usage when sharing operational amplifiers between stages, which contradicts the goal of reducing layout area.
Innovation Solution
The solution involves sharing sub-ADC and sub-DAC components between sequential stages or channels in a pipelined ADC architecture, allowing components to alternate between sampling and amplifying states, thereby reducing the overall layout area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If operational amplifiers are shared between stages to reduce layout area, then layout area is reduced, but power consumption increases in high-speed applications
Solution Approach 1:
The patent applies dynamics by making the operational amplifiers dynamically shareable between stages through timing-based control. The same operational amplifier can serve different stages at different times, with its function dynamically adjusted based on the operational phase (sampling vs. amplifying). This dynamic sharing reduces layout area while the timing control ensures that in high-speed applications, the amplifier can be dedicated to amplifying operations when needed, thus controlling power consumption.
Solution Approach 2:
The patent implements periodic action through the alternating sampling and amplifying phases. Operational amplifiers are periodically switched between different functional stages, with each amplifier serving multiple stages in a periodic manner. This periodic sharing allows area reduction while maintaining performance by ensuring that during high-speed amplifying phases, the amplifier is properly dedicated to that function, thus balancing area and power consumption.
2Speed
If larger components are used to achieve high-speed operation, then speed is improved, but layout area increases
Solution Approach 1:
The patent applies universality by designing operational amplifiers that can perform multiple functions across different stages. Instead of having dedicated amplifiers for each stage, the same amplifier can serve multiple stages by alternating between sampling and amplifying operations. This multi-functionality allows the use of smaller, faster components that can be dynamically reassigned, achieving high speed without proportionally increasing layout area.
Solution Approach 2:
The patent merges the functions of multiple operational amplifiers into a single shared resource. By combining the sampling and amplifying functions into a time-multiplexed operational amplifier, the patent reduces the total number of components needed. This merging allows high-speed operation to be achieved with fewer, optimized components rather than multiple larger dedicated components, thus reducing layout area while maintaining speed performance.
Data Source
AI summary
In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second stage. The first and second stages are configured to share a sub-ADC and a sub-digital-to-analog converter.