Pipelined ADC Sub-DAC Segmentation for Lower Capacitor Count
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Solution Overview
Problem
The exponential growth of switched capacitor arrays in pipelined analog-to-digital converters with increasing resolution leads to increased area and power consumption, limiting the speed of analog-to-digital conversion.
Innovation Solution
The proposed pipelined analog-to-digital converter simplifies the switched capacitor circuit by splitting the digital output of the N-bit sub-analog-to-digital conversion module into two parts, corresponding to two sub-digital-to-analog conversion modules, reducing the number of switched capacitors and improving processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the pipelined ADC is increased, then the measurement precision is improved, but the number of switched capacitors increases exponentially leading to increased area and power consumption
Solution Approach 1:
The patent segments the single sub-DAC into two separate sub-DACs (first and second sub-digital-to-analog conversion modules), each handling a portion of the digital signals. This segmentation reduces the number of switched capacitors required in each sub-DAC from 2^N to 2^(N-1), thereby reducing the total area of the switched capacitor array while maintaining the same conversion resolution
Solution Approach 2:
The patent introduces a new structural dimension by splitting the digital signal processing into two parallel paths (first and second sub-DACs processing different sets of digital signals). This dimensional change allows the system to achieve the same resolution with reduced complexity in each individual path, avoiding the exponential growth of switched capacitors
2Measurement precision
If the resolution of the pipelined ADC is increased, then the measurement precision is improved, but the number of switched capacitors increases exponentially leading to increased power consumption
Solution Approach 1:
By segmenting the sub-DAC into two smaller sub-DACs, each with fewer switched capacitors (2^(N-1) instead of 2^N), the patent reduces the total number of switched capacitors by 50%. Since power consumption in switched capacitor circuits is directly proportional to the number of switched capacitors, this segmentation achieves a 50% reduction in power consumption while maintaining the same conversion resolution
3Measurement precision
If the number of switched capacitors is increased to achieve higher resolution, then the measurement precision is improved, but the processing speed decreases due to increased circuit complexity
Solution Approach 1:
The patent segments the digital signal processing into two parallel paths, each with reduced complexity (fewer switched capacitors). This segmentation allows each path to operate faster while maintaining the same overall resolution, thereby improving the processing speed by 1-2 times compared to a traditional single sub-DAC architecture with exponential complexity
4Device complexity
If the number of switched capacitors is reduced to decrease area and power consumption, then the device complexity is reduced, but the measurement precision may be compromised
Solution Approach 1:
The patent merges the outputs of two parallel sub-DAC paths through the switched capacitor amplification module, which performs differential operations and amplification. This merging strategy allows each individual sub-DAC to have reduced complexity (fewer switched capacitors), while the combined output maintains the full resolution through the differential processing and amplification by a factor of 2^(N-1)
Data Source
AI summary
In a pipelined analog-to-digital converter, at least one pipeline stage includes an N-bit sub-analog-to-digital conversion module, a first sub-digital-to-analog conversion module, a second sub-digital-to-analog conversion module, and a switched capacitor amplification module. The first sub-digital-to-analog conversion module and the second sub-digital-to-analog conversion module respectively receive and process 2N−1 digital signals, which correspondingly require 2*2N−1 switched capacitors. In a pipeline stage based on a structure of “N-bit sub-analog-to-digital conversion module+sub-digital-to-analog conversion module+subtractor+multiplier”, the non-inverting input and the inverting input of the differential input comparison are completely symmetrical, which correspondingly requires 2*2N switched capacitors.