Pipelined ADC Background Calibration for Comparator Threshold Mismatch
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Solution Overview
Problem
Pipelined analog-to-digital converters (ADCs) face performance degradation due to mismatch errors in resistor ladders and comparator offsets, leading to output nonlinearity and increased latency, which requires calibration that interrupts normal operation and increases chip area and power consumption.
Innovation Solution
A self-calibrating pipelined ADC system that adjusts sub-ADC comparator thresholds using digital codes from subsequent stages to correct for threshold shifts without additional components in the signal path, allowing for background calibration and reducing the size and power requirements of the resistor ladder and comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If foreground calibration is performed to correct mismatch errors, then output nonlinearity is reduced, but normal ADC operation is interrupted and latency increases
Solution Approach 1:
The patent performs calibration in the background during normal operation rather than requiring a separate foreground calibration phase. The system continuously monitors comparator outputs and adjusts resistor values dynamically, eliminating the need to interrupt ADC operation for calibration.
Solution Approach 2:
The calibration process runs concurrently with normal ADC conversion operations. The system maintains continuous calibration adjustment while simultaneously performing conversions, ensuring both calibration and operation proceed without interruption to each other.
2Measurement precision
If circuitry size is increased to improve matching, then mismatch errors are reduced, but chip area and power consumption increase
Solution Approach 1:
The patent implements self-calibration where the ADC system automatically detects and corrects its own mismatch errors without requiring external calibration equipment or additional dedicated calibration circuitry. The calibration function is integrated into the existing ADC structure, using the same comparators and resistors that perform normal conversion.
Solution Approach 2:
The system dynamically adjusts resistor values in the resistor ladder based on detected mismatch errors. By changing the resistance parameters in real-time, the system corrects matching errors without requiring additional physical components or increased chip area.
3Measurement precision
If circuitry size is increased to improve matching, then output nonlinearity is reduced, but power consumption increases
Solution Approach 1:
The integrated self-calibration mechanism eliminates the need for separate calibration circuits that would consume additional power. The calibration function is performed using the existing ADC components, avoiding the power penalty of dedicated calibration hardware.
Solution Approach 2:
The system corrects nonlinearity by dynamically adjusting resistor values through digital control rather than using larger, more power-consuming analog correction circuits. This parameter-based approach reduces power consumption while maintaining correction effectiveness.
Data Source
AI summary
A method and apparatus for calibrating a pipelined analog-to-digital converter (ADC) is disclosed. A method includes reading a first output level from a first sub-ADC, reading one or more additional output levels from one or more additional sub-ADCs, combining the one or more additional output levels from the one or more additional sub-ADCs into a combined output level, and adjusting a comparator threshold of the first sub-ADC when the first output level and the combined output level meet a set of predetermined conditions.