Pipelined ADC Timing Without Input Sample/Hold
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Solution Overview
Problem
Pipelined analog to digital converters (ADCs) require sample and hold circuits that increase die size and limit dynamic range due to the need for buffer amplifiers and additional sample/hold circuits, leading to errors and increased power consumption.
Innovation Solution
A pipelined ADC design without an input sample/hold circuit, using an amplifier gain of (2^n)/4 in the first stage and reference scaling in subsequent stages, along with additional comparators for dynamic range expansion and error correction, and adjustable clock delays to minimize voltage differential errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an input sample/hold circuit is used in pipelined ADC, then sampling accuracy is improved, but die area increases and dynamic range is limited
Solution Approach 1:
The patent removes the input sample/hold circuit from the first stage of the pipelined ADC, extracting this component out of the system. This eliminates the need for the large capacitor and buffer amplifier associated with input sampling, thereby reducing die area while maintaining conversion accuracy through alternative timing synchronization methods
Solution Approach 2:
The patent makes the existing stage sample/hold circuits serve dual functions: they both sample their respective signals and provide timing reference for the entire conversion process. This multi-functionality eliminates the need for a separate input sample/hold circuit, reducing die area while maintaining sampling accuracy
2Ease of operation
If buffer amplifier is used in input sample/hold circuit, then signal buffering is improved, but dynamic range is limited and power consumption increases
Solution Approach 1:
The patent extracts and removes the buffer amplifier from the input sample/hold circuitry. By eliminating this high-power component, the design reduces power consumption while achieving signal buffering through the inherent high-impedance nodes of the flash ADC comparators and the timing-synchronized sampling approach
3Measurement precision
If additional sample/hold circuits are added for timing synchronization, then conversion accuracy is improved, but device complexity increases
Solution Approach 1:
The patent makes the existing stage sample/hold circuits perform multiple functions: they sample their respective signals and simultaneously provide timing reference for the entire conversion process. This multi-functionality achieves timing synchronization and conversion accuracy without adding extra sample/hold circuits, thereby avoiding increased device complexity
Solution Approach 2:
The patent merges the timing reference function with the sampling function by using the same clock signal and sample/hold circuitry for both purposes. This consolidation achieves synchronization without requiring separate timing circuits, reducing overall device complexity
Data Source
AI summary
The first stage of a plurality of stages in a pipelined analog to digital converter couples its input analog signal to both a first and second sample and hold (S/H). The first S/H output is coupled to the input of a multiplying digital to analog converter (MDAC) of the first stage, and the second S/H output is coupled to a flash ADC of the first stage. The delay of the second S/H is longer than the delay of the first S/H, and the clock edge of the second S/H is delayed an adjustable amount with respect to the clock edge of the first S/H, so as to minimize the difference in held voltages at the outputs of the two S/Hs in the presence of an input signal having high slew rate. The residue voltage of the first stage is amplified in the MDAC by 2̂(n−2) where n is the number of bits in the stage. The second stage flash ADC has a range of normal threshold voltage levels substantially half that of the first stage, and a plurality of added threshold voltage levels and corresponding comparators above and below the normal highest and lowest threshold voltages, thereby increasing dynamic range and providing over range and under range indications facilitating adjustment of the delay of the clock edge of the first stage second S/H.