Pipelined Multi-Operand Adder Carry Chain Segmentation
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Solution Overview
Problem
Long ripple carry adder chains in integrated circuits for adding multi-digit binary numbers lead to increased operating cycle times, as signal propagation takes longer, which can slow down the entire circuit operation.
Innovation Solution
Introduction of pipelining registers into both the ripple carry chain and redundant form carry bit signal routing, allowing signals to be captured and output in separate clock cycles, thereby breaking long signal propagation paths and enabling faster operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a long ripple carry adder chain is used to add very long binary numbers, then the addition capability is improved, but the signal propagation time increases and operating cycle time increases
Solution Approach 1:
The patent divides the long ripple carry adder chain into multiple segments or stages, each handling a portion of the binary number addition. By segmenting the adder chain, the signal propagation distance in each segment is reduced, thereby decreasing the operating cycle time while maintaining the capability to add very long binary numbers through cascaded segments.
Solution Approach 2:
The patent introduces pipelining registers that capture and hold intermediate carry signals at specific stages of the addition process. This preliminary action allows subsequent stages to begin processing before previous stages complete, overlapping the execution of multiple addition operations and reducing the overall operating cycle time.
2Loss of time
If pipelining registers are introduced into the ripple carry chain, then the operating cycle time is reduced, but the device complexity increases
Solution Approach 1:
The patent strategically places pipelining registers at specific segmentation points within the ripple carry chain, dividing the long adder into manageable stages. This segmented approach reduces the critical path delay and operating cycle time while minimizing the total number of registers required, thus balancing performance improvement with acceptable device complexity.
Solution Approach 2:
The pipelining registers are designed to serve multiple functions: they act as carry signal storage elements, enable stage synchronization, and facilitate overlapping of addition operations. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving significant operating cycle time reduction.
Data Source
AI summary
Circuitry for adding together three long numbers may include the formation of redundant form sum bit signals and redundant form carry bit signals. These signals may be finally combined in a ripple carry adder chain that produces sum bit output signals and ripple carry bit signals. Both a ripple carry bit signal and a redundant form carry bit signal must be passed from the circuitry performing each place of the addition to the circuitry performing the next-more-significant place of the addition. Various techniques are disclosed for facilitating subdividing long chains of such circuitry, as well as possibly including (between such subdivisions) “pipeline” registers for both ripple and redundant form carry bit signals.