Pipelined Adder Circuit for Long-Integer Multiplication
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Solution Overview
Problem
Existing cryptographic devices face inefficiencies in performing long integer multiplications, particularly in cryptographic algorithms like RSA, due to the need for quick and repeated execution of long integer modular multiplications, which are slowed by conventional summation methods such as Wallace trees that require more hardware and introduce delays.
Innovation Solution
A pipelined adder circuit with a network of carry-save adders arranged in columns, where the number of adders varies by bit position, and an output stage that feeds back carry bits to reduce delays and allow simultaneous processing of subsequent calculations, optimizing the summation of addends with adaptive tree structures to minimize hardware and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional Wallace trees are used for summation, then the multiplication can be performed, but the hardware complexity increases and processing delay is introduced
Solution Approach 1:
The patent segments the long integer multiplication process into multiple parallel stages, where each stage processes a portion of the intermediate results. The adder network is divided into multiple levels that operate concurrently, with each level handling specific bit positions and addend combinations. This segmentation enables parallel processing of summation operations, significantly reducing the overall computation time while maintaining manageable hardware complexity at each stage.
Solution Approach 2:
The patent employs a dynamic adder network configuration where the number of adders at each level is adaptively determined based on the actual number of addends required at that stage. Rather than using a fixed, maximum-capacity Wallace tree structure, the network dynamically adjusts the number of active adders according to the varying number of intermediate results that need summation at different bit positions. This dynamic approach optimizes hardware utilization and reduces unnecessary complexity.
2Device complexity
If a fixed number of adders is used in the network, then the hardware structure is simplified, but the processing speed decreases due to unnecessary levels
Solution Approach 1:
The patent applies local quality by configuring the adder network with varying numbers of adders at different levels and bit positions, rather than using a uniform structure throughout. Each level of the adder network is specifically designed with the precise number of adders needed to handle the local summation requirements at that stage. This localized optimization ensures that no unnecessary adder levels are present, maximizing processing speed while keeping the hardware structure appropriately complex only where required.
3Loss of time
If carry bits are retained and fed back, then subsequent calculations can commence earlier, but the network structure becomes more complex
Solution Approach 1:
The patent implements a feedback mechanism where carry bits generated at each addition stage are retained and fed back as inputs to subsequent multiplication stages. This feedback loop allows the network to maintain an ongoing calculation state, enabling the next multiplication operation to commence before the previous one is fully complete. The carry bits from prior operations are seamlessly integrated into the next stage's computation, eliminating idle time between operations and significantly reducing overall processing delay.
Data Source
AI summary
An adder circuit for multiplying two long integers deploys a network of adders for summing a succession of words of the long integers to generate intermediate results. The number of addends varies as a function of bit position and the network of adders is designed to reduce the number of levels of adders in the network according to a maximum number of expected addends. A number of strategically placed extra adders may be positioned in the network to further reduce the number of levels. An output stage may be provided that adds sum and carry outputs of the network and retains a most significant bit for use with a subsequent calculation output of the network. The network may be configured so that a subsequent calculation by the network can commence before the previous calculation has been completed, the output of the previous calculation being fed back to the network at an intermediate level and its lowest (output) level.