Pipelined ATE Architecture for Test Throughput
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Solution Overview
Problem
Automatic test equipment (ATE) systems face a trade-off between throughput and cost, with shared architectures leading to under-utilization of test resources and increased latency due to synchronous test signal broadcasting and the need for multiple test resources in per site architectures, which are costly and inefficient with varying pin counts.
Innovation Solution
A pipelined testing architecture where a shared processor generates stimulus, and dedicated processors handle data transfer and polling/interrupt functions for each device under test (DUT), allowing the shared hardware to generate the next stimulus without waiting for all DUTs to complete, thereby increasing throughput while minimizing incremental cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a shared ATE architecture is used to reduce cost, then capital expenditure is reduced, but test throughput decreases due to under-utilization of test resources and synchronous broadcasting requirements
Solution Approach 1:
The patent segments the ATE architecture into shared components (test resource, pattern generator) and dedicated components (processor per DUT, interrupt handling). Each DUT has its own processor that can independently manage test execution and interrupt responses, while sharing the pattern generator and other test resources. This segmentation allows asynchronous operation where each DUT progresses through its test sequence independently, eliminating the throughput bottleneck of synchronous broadcasting while maintaining cost efficiency through resource sharing.
2Adaptability or versatility
If synchronous broadcasting of test signals is used in shared architecture, then resource sharing is enabled, but latency increases due to waiting for all DUTs to be ready
Solution Approach 1:
The patent implements dynamic test execution where each DUT operates at its own pace with its dedicated processor. The system transitions from static synchronous broadcasting to dynamic asynchronous operation. Each processor can independently advance its DUT through the test sequence, send and receive interrupts, and manage its own timing without being constrained by other DUTs. This dynamic approach maintains resource sharing capability while eliminating the time loss associated with waiting for all DUTs to synchronize.
3Productivity
If a per site architecture with dedicated test resources is used for each DUT, then test throughput improves, but capital expenditure increases due to multiple test resources
Solution Approach 1:
The patent applies universality by making test resources multi-functional. The shared pattern generator and test resources can serve multiple DUTs simultaneously, with each DUT having its own processor to manage its specific test requirements. This allows a single test resource to perform multiple functions across different DUTs, achieving the throughput benefits of dedicated resources while maintaining the cost efficiency of resource sharing. Each processor acts as a universal controller that can manage any DUT connected to the shared resources.
Data Source
AI summary
A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.