Pipelined Authentication Circuitry With Decimated Hash Inputs
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Solution Overview
Problem
Existing GCM processes in authentication systems face challenges with high manufacturing costs due to large combinational logic and high input complexity, leading to reduced throughput and increased latency, especially in recursive processing formats.
Innovation Solution
Implementing decimation circuitries followed by recursive circuitry in a pipelined architecture to reduce sampling rates, allowing for pipelined multiplication without affecting throughput, thereby improving processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel computation of Galois field multiplication is used for authentication, then throughput is increased, but device complexity and manufacturing cost increase due to large combinational logic
Solution Approach 1:
The patent segments the authentication processing into distinct functional blocks: a key stream generator circuitry for encryption/decryption operations and a separate hash function circuitry for authentication tag generation. This segmentation allows each block to be optimized independently, reducing the complexity of individual combinational logic while maintaining overall throughput performance.
Solution Approach 2:
The patent employs preliminary action by using a key stream generator that processes data in advance through counter mode encryption, generating encrypted data streams before the authentication hash computation. This preliminary processing reduces the complexity of subsequent authentication operations by pre-transforming the data into a form that requires fewer complex combinational logic operations.
2Reliability
If recursive processing format is used in GCM process, then authentication tag generation is achieved, but latency increases and throughput decreases
Solution Approach 1:
The patent divides the authentication process into sequential stages: first the key stream generator circuitry processes the input data through counter mode encryption, then the hash function circuitry receives the encrypted data and generates the authentication tag. This segmentation eliminates the need for recursive processing formats, allowing each stage to operate independently with reduced latency.
Solution Approach 2:
The patent ensures continuous processing by having the key stream generator circuitry continuously generate encrypted data streams that are immediately fed into the hash function circuitry. This continuous pipeline operation eliminates idle time and waiting periods associated with recursive processing, maintaining steady throughput while reducing overall latency.
3Productivity
If large combinational logic is used in authentication system, then processing capability is enhanced, but manufacturing cost increases
Solution Approach 1:
The patent segments the authentication system into two main circuitries: a key stream generator circuitry for encryption operations and a hash function circuitry for authentication. This segmentation allows each circuitry to be designed with optimized, smaller-scale combinational logic rather than requiring one large complex logic block, thereby reducing manufacturing costs while maintaining processing capability.
Solution Approach 2:
The patent designs the key stream generator circuitry to perform multiple functions including counter mode encryption and data transformation, which are then fed into the hash function circuitry. This multi-functionality reduces the need for separate dedicated circuits for each operation, lowering overall manufacturing complexity and cost while preserving processing capability.
Data Source
AI summary
An authentication device for a communication device includes key stream generator circuitry and hash function circuitry. The key stream generator circuitry receives a first input data stream and generates a first data stream output signal based on the first input data stream and an encryption key. The first input data stream is associated with a first data rate. The hash function circuitry receives the first data stream output signal from the key stream generator circuitry. The hash function circuitry includes first decimation circuitry and recursive circuitry. The first decimation circuitry receives the first data stream output signal, and combines adjacent data words of the first data stream output signal to generate a first decimated output signal having a second data rate. The second data rate is less than the first data rate. The recursive circuitry generates an authentication tag based on the first decimated output signal.


