Pipelined BCH Error Correction Circuit for Faster Memory Decoding
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Solution Overview
Problem
Error correction circuits for nonvolatile memory devices face increased decoding time due to recursive operations in BCH code decoding, leading to performance degradation, especially in devices with high error rates like PCRAM, MRAM, NFGM, and RRAM, where cell interference and narrow read margins result in higher error rates.
Innovation Solution
An error correction circuit is designed to operate in a pipelined manner, including a syndrome calculator, error location polynomial calculator, and error corrector, capable of generating syndromes, error locations, and correcting errors within a single clock cycle, using simplified Berlekamp-Massey algorithms and combinational logic to reduce decoding time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BCH code decoding is performed using traditional recursive algorithms, then error correction capability is improved, but decoding time increases significantly
Solution Approach 1:
The error correction circuit is divided into multiple independent pipeline stages: syndrome calculation unit, error location polynomial calculation unit, error location calculation unit, and error correction unit. Each stage processes data independently and simultaneously, enabling parallel computation of the BCH decoding algorithm while maintaining full error correction capability.
Solution Approach 2:
The circuit implements a dynamic pipeline architecture where data flows through multiple clock cycles across different processing stages. Each stage produces results at different times, and the pipeline continuously processes new data blocks, achieving both high-speed operation and complete error correction functionality.
2Quantity of substance
If multi-level cell techniques are used to increase bits per cell, then integration density is improved, but error rate increases due to cell-to-cell interference
Solution Approach 1:
The error correction circuit is specifically designed to handle high error rates by implementing a pipeline architecture that can process and correct multiple errors per codeword. The syndrome calculation and error location polynomial calculation stages are optimized to efficiently identify and correct errors arising from MLC cell interference, maintaining data reliability despite increased integration density.
3Quantity of substance
If advanced process techniques are used to reduce feature size, then integration density is improved, but reliability degrades due to manufacturing variability
Solution Approach 1:
The circuit incorporates error correction capabilities that account for manufacturing variability by designing the pipeline stages to handle a wide range of error patterns. The syndrome calculation unit and error location polynomial calculator are configured to detect and correct errors resulting from process variations, ensuring reliable operation despite reduced feature sizes and increased integration density.
4Productivity
If pipelining is implemented to reduce decoding time, then processing speed is improved, but circuit complexity increases
Solution Approach 1:
The complex BCH decoding algorithm is segmented into four distinct pipeline stages, each performing a specific function. This segmentation allows the use of simpler, dedicated circuitry in each stage rather than a single complex sequential implementation, reducing overall circuit complexity while achieving high processing speed through parallel operation.
Solution Approach 2:
The pipeline registers and data buses are designed to be universal, handling multiple types of data (syndromes, polynomial coefficients, error locations) through the same physical infrastructure. This multi-functionality reduces the need for separate dedicated circuits for each data path, thereby reducing overall circuit complexity while maintaining high processing speed.
Data Source
AI summary
An error correction circuit includes a syndrome calculator suitable for generating syndromes from an “n”-bit codeword for a single unit of time, an error location polynomial calculator suitable for generating error location polynomial coefficients based on the syndromes provided for the single unit of time, an error location calculator suitable for calculating error locations based on the error location polynomial coefficients for the single unit of time, and an error corrector suitable for correcting errors of the codeword based on the error locations for the single unit of time. The error correction circuit operates in a pipelining manner.