Pipelined Buffer Interconnect for Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data transfer methods in computational devices are inefficient due to processor bandwidth consumption and bus contention, and lack real-time error detection and pattern recognition capabilities.
Innovation Solution
The implementation of a pipelined buffer interconnect system that uses dedicated buffers and buses to streamline data transfer between data sources and sinks, along with a trigger core for pattern detection and event triggering, minimizing processor involvement and enabling concurrent data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer is initiated and managed by an application running on a processor, then data transfer can be performed, but processor bandwidth is consumed and transfer speed is slowed due to bus arbitration
Solution Approach 1:
The patent extracts the data transfer management function from the processor by introducing a dedicated DMA engine that operates independently. The DMA engine handles data transfer initiation and management without requiring processor intervention, thereby freeing processor bandwidth and eliminating bus arbitration delays that occur when the processor manages transfers.
Solution Approach 2:
The patent introduces a DMA engine as an intermediary between the processor and memory/system bus. This intermediary handles all data transfer operations, allowing the processor to focus on computation while the DMA engine manages data movement, thus resolving the conflict between processor bandwidth availability and data transfer speed.
2Adaptability or versatility
If DMA engines are used for data transfer, then processor bandwidth is freed, but DMA engines are limited to transfers between main memory and hard disk drives
Solution Approach 1:
The patent enhances the DMA engine to perform multiple functions beyond traditional memory-to-disk transfers. The extended DMA engine can now handle transfers between any two memory regions, support different data formats, and work with various peripheral devices, making it a universal data transfer solution that maintains high speed while increasing versatility.
3Reliability
If error checking mechanisms such as CRC are used, then errors can be detected, but errors are only detected at the end of data transfer
Solution Approach 1:
The patent implements preliminary error detection by placing checksum calculation and verification logic at intermediate points during data transfer, rather than only at the end. This allows errors to be detected in real-time during the transfer process, enabling immediate corrective action and preventing completion of corrupted transfers.
4Difficulty of detecting and measuring
If conventional data transfer methods are used, then data can be transferred, but no mechanisms exist to detect real-time patterns in data being transferred
Solution Approach 1:
The patent introduces pattern detection logic as an intermediary component that monitors data during transfer through the extended DMA engine. This intermediary analyzes data patterns in real-time without interfering with the transfer speed, providing enhanced monitoring capability while maintaining efficient data movement.
Data Source
AI summary
A computer implemented method to transfer data from a data source to a data sink is provided. The method includes the steps of allocating a first buffer to the data source and locking the first buffer so as to enable only the data source to transfer data to the first buffer. The method further includes the steps of unlocking the first buffer and granting access to the data sink to read from the first buffer. The method also includes the steps of allocating a second buffer to the data source, locking the second buffer and enabling the data source to write data to the second buffer while enabling the data sink to read data from the first buffer, thereby pipelining data transfer from the data source to the data sink.