Pipelined Burst Error Correction Decoder With Lower Gate Count
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Solution Overview
Problem
Conventional implementations of burst error correction codes, such as the Fire code, require a large number of gates in integrated circuits, leading to increased cost and power consumption due to their complex design and multiple instances in high-speed serializer/deserializers.
Innovation Solution
A pipelined system and method for efficient parallel implementation of burst error correction codes that simultaneously perform syndrome computation, error trapping, and error correction using Galois Field arithmetic, significantly reducing the design size to approximately 1/20th that of conventional approaches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional parallel implementation of Meggitt Error Trapping Decoder is used, then error correction capability is achieved, but gate count and implementation complexity increase significantly
Solution Approach 1:
The decoder is divided into multiple functional pipelines: syndrome computation pipeline, error trapping pipeline, and error correction pipeline. Each pipeline processes different aspects of the decoding operation independently and in parallel, reducing the complexity of any single pipeline while maintaining overall error correction capability.
Solution Approach 2:
The implementation uses dynamic pipeline registration and configurable pipeline stages that can be adjusted based on the specific Fire code parameters (m values). This allows the same hardware structure to adapt to different code configurations without requiring complete redesign, reducing overall gate count.
2Reliability
If multiple instances of decoder are used in high-speed serializer/deserializers, then error correction coverage is improved, but total power consumption and cost increase
Solution Approach 1:
The decoder design is created as a universal, parameter-configurable module that can handle different Fire code variants (e.g., OIF-CEI-P, 10GBASE-KR) through configuration rather than hardware duplication. This multi-functionality allows a single decoder instance to serve multiple protocol requirements, reducing the number of instances needed.
Solution Approach 2:
Multiple decoding functions are merged into a single integrated pipeline structure where syndrome computation, error trapping, and error correction operations are combined in a unified hardware architecture. This merging eliminates redundant circuitry that would exist in separate decoder instances.
3Speed
If conventional parallel implementation is used, then decoding speed is achieved, but design size becomes excessively large
Solution Approach 1:
Syndrome computation is performed in advance in a dedicated pipeline stage before error trapping and correction. This preliminary computation prepares the necessary data structures and syndrome values ahead of time, enabling faster subsequent error correction operations without requiring larger hardware resources.
Solution Approach 2:
The implementation transitions from a two-dimensional array of parallel decoders to a three-dimensional pipeline structure with multiple processing stages flowing through shared resources. This dimensional change allows time-multiplexed use of hardware resources, achieving high throughput with reduced area.
Data Source
AI summary
The present invention provides systems and methods for an efficient, parallel implementation of burst error correction codes, such as the Fire code. The present invention includes a FEC decoder which is pipelined to simultaneously perform syndrome computation, error trapping and syndrome normalization, and error correction. The pipelined implementation can apply to shortened and full-length codes. Advantageously, the present invention yields a design which is approximately 1/20th the size of conventional parallel approaches.