Pipelined Byte Substitution for AES Hardware
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Solution Overview
Problem
The implementation of the Advanced Encryption Standard (AES) in hardware faces challenges in efficiently performing byte substitution operations due to the complexity of Galois Field (GF) operations, particularly inversion in GF(256), which is difficult to implement quickly and size-efficiently.
Innovation Solution
A cryptographic device with pipelined stages that perform mathematical operations using Galois Field operations, including byte substitution and column mixing, to efficiently process AES encryption and decryption, utilizing pipeline registers to balance delays and reduce area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Galois Field operations (particularly inversion in GF(256)) are implemented in hardware for AES byte substitution, then encryption and decryption functionality is achieved, but the implementation becomes difficult to execute quickly and consumes excessive area
Solution Approach 1:
The byte substitution operation is divided into two separate pipeline stages: the first stage performs inversion in GF(256) to produce an intermediate value, and the second stage performs multiplication by the polynomial x+1 in GF(256) to produce the final substituted byte. This segmentation allows each stage to be simpler and faster, with the intermediate value being stored in a pipeline register between stages.
Solution Approach 2:
The inversion operation is performed as a preliminary action in the first pipeline stage, producing an intermediate value that is then used in the second stage for the multiplication operation. This preliminary action allows the complex inversion to be completed before the final substitution, enabling optimized hardware implementation of each individual operation.
2Speed
If traditional non-pipelined byte substitution is used, then area consumption is reduced, but processing speed becomes slow
Solution Approach 1:
The byte substitution is implemented as a dynamic pipelined structure where data flows through multiple stages with pipeline registers. This allows the hardware to process multiple bytes concurrently at different pipeline stages, increasing throughput while keeping each individual stage relatively simple and area-efficient.
Solution Approach 2:
The pipelined structure enables periodic processing of bytes through the two stages, with each stage operating in a repeating cycle. This periodic action through the pipeline allows sustained high processing speed while maintaining simple, area-efficient stage designs that can be clocked at high frequencies.
3Area of stationary object
If byte substitution is performed in a single stage, then pipeline delays are minimized, but area requirements increase due to the complexity of GF operations
Solution Approach 1:
The byte substitution is segmented into two pipeline stages with an intermediate value stored in a pipeline register. This segmentation reduces the area of each individual stage by dividing the complex GF operations into simpler sub-operations, while the overall processing time is managed through the pipelined structure that allows concurrent processing.
Solution Approach 2:
An intermediate value is introduced as a mediator between the inversion operation in the first stage and the multiplication operation in the second stage. This intermediate value is stored in a pipeline register and serves as the bridge between the two simpler operations, allowing area-efficient implementation of each stage while maintaining correct cryptographic functionality.
Data Source
AI summary
A cryptographic device includes first and second pipeline stages and a pipeline register. The first pipeline stage includes a first byte substitution module configured to (i) receive a first data block including multiple bytes, (ii) perform predetermined mathematical operations on each of the bytes of the first data block, and (iii) for each of the bytes of the first data block, output an intermediate value based on the predetermined mathematical operations. The pipeline register is configured to store the intermediate values. The second pipeline stage includes a second byte substitution module configured to (i) receive the stored intermediate values from the pipeline register, and (ii) generate an output data block, for each intermediate value of the stored intermediate values, by performing predetermined mathematical operations on the intermediate value to generate a corresponding replacement byte of the output data block.