Pipelined Comparator Circuit for High-Speed Max Min Detection
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Solution Overview
Problem
Existing hardware circuits for finding the maximum or minimum of a set of numbers are limited by the number of logic levels between registers, which restricts clock speed and efficiency.
Innovation Solution
The apparatus includes multiple comparators with latency of at least one clock cycle, combinatorial logic, and switching means to determine and update the best score based on previous comparisons, reducing the number of logic levels and increasing clock speed by using pipelined comparators and feedback mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple logic levels are used between registers in the hardware circuit, then the circuit can perform comparison and switching operations, but the clock speed is limited by the number of logic levels
Solution Approach 1:
The patent segments the comparison operation into two independent parallel comparators: a first comparator that compares the current number with the current best score, and a second comparator that compares the current number with a previous input number. This segmentation allows each comparator to operate independently, reducing the critical path length and enabling higher clock speeds while maintaining the necessary comparison functionality.
Solution Approach 2:
The patent performs preliminary comparison actions by using the second comparator to compare the current number with a previous input number before the main switching decision is made. This preliminary action provides advance information about whether the current number could potentially become the new best score, allowing the switching means to make faster decisions without waiting for multiple sequential logic levels to complete.
2Reliability
If feedback is used to update the current best score, then the circuit can maintain accurate best score tracking, but the clock speed is limited by the feedback path through the comparator and switch
Solution Approach 1:
The feedback mechanism is segmented into separate functional blocks: the first comparator handles the comparison of current number with current best score, the second comparator handles the comparison with previous input, and the switching means handles the update decision. This segmentation allows the feedback path to be optimized independently, maintaining accurate best score tracking while reducing the critical path length that limits clock speed.
Solution Approach 2:
The patent implements feedback by using the output of the first comparator to control the switching means, which then updates the current best score register. This feedback mechanism ensures accurate best score tracking while the parallel structure of the comparators and the combinatorial logic reduce the feedback path delay, allowing faster clock speeds.
3Productivity
If a single comparator is used to compare current number with current best score, then the circuit is simple, but it cannot determine the maximum or minimum efficiently without multiple logic levels
Solution Approach 1:
The patent segments the determination of maximum or minimum into two parallel comparison paths: the first comparator compares the current number with the current best score to determine if an update is needed, while the second comparator compares the current number with the previous input number to provide additional context. This segmentation enables efficient maximum or minimum determination by processing both comparisons simultaneously, improving productivity while the structured approach keeps device complexity manageable.
Solution Approach 2:
The second comparator performs a preliminary comparison of the current number with the previous input number before the final switching decision is made. This preliminary action provides advance information that helps the switching means make faster and more accurate decisions about whether to update the current best score, improving the efficiency of maximum or minimum determination without requiring excessive logic levels.
Data Source
AI summary
An apparatus for determining a best number, representing a maximum or minimum of a set of numbers, includes a first comparator 3 having a latency of at least one clock cycle to compare a current number with a current best score and to output a corresponding first comparator signal 7 and at least a second comparator 13 having a latency of at least one clock cycle to compare the current number with any other input number compared with a current best number while the current number was being processed through the apparatus and to output at least a corresponding second comparator signal 18. A combinatorial logic block 15 receives the comparator signals and outputs a corresponding signal 20 dependent thereon and on a flag signal 21 received from flagging means arranged to flag whether the current best number was updated for one or more preceding input numbers while the current number was being processed. A switch 6 outputs either the current best number, or the current number, as a new current best number, dependent upon the combinatorial logic block signal. A resultant reduction in logic steps processed in each clock cycle permits an increased clock frequency compared with the prior art.