Pipelined CORDIC Processor for QR Decomposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing MIMO systems face inefficiencies in channel processing computations due to the need for complex multipliers and arithmetic engines, particularly in performing orthogonal matrix transformations like QR Decomposition and SVD, which are not adequately addressed by current CORDIC processor architectures.
Innovation Solution
A programmable multi-stage pipelined CORDIC processor architecture that allows for flexible and iterative computation of orthogonal transformations, enabling efficient QR decomposition and other matrix operations by reusing stages and applying Given's rotation method, suitable for MIMO signal processing and other mathematical computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex multipliers and arithmetic engines are used for orthogonal matrix transformations, then computational accuracy is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent replaces complex multipliers and arithmetic engines with a CORDIC-based iterative computation system that uses simple shifters, adders, and sign multipliers. The CORDIC algorithm substitutes traditional mechanical multiplication operations with coordinate rotation iterations, achieving the same computational accuracy through a less complex architectural approach.
Solution Approach 2:
The patent divides the orthogonal matrix transformation into multiple iterative stages, where each stage performs a simplified coordinate rotation. Instead of using a single complex computation unit, the system segments the transformation into sequential micro-operations that can be executed by simpler components, reducing overall device complexity while maintaining accuracy.
2Productivity
If custom CORDIC architectures are designed for specific matrix sizes, then processing efficiency for that size is improved, but adaptability to different matrix sizes deteriorates
Solution Approach 1:
The patent designs a universal CORDIC processor architecture that can handle orthogonal transformations for matrices of any size. The system uses programmable control logic and iterative computation stages that can be configured for different matrix dimensions, eliminating the need for custom architectures for each specific size while maintaining high processing efficiency across all applications.
Solution Approach 2:
The patent implements a dynamic and reconfigurable CORDIC processor where the number of iterative stages and control parameters can be adjusted based on the input matrix size. This dynamic adaptability allows the same hardware architecture to efficiently process different matrix dimensions without requiring custom design for each case.
3Adaptability or versatility
If iterative CORDIC computation is used, then flexibility and adaptability are improved, but computation time increases
Solution Approach 1:
The patent implements a pipelined CORDIC processor where multiple iterative stages operate continuously and concurrently. While each individual transformation requires iterative computation, the pipeline architecture ensures that useful action continues without interruption by overlapping the execution of multiple transformations, thereby reducing the overall computation time penalty associated with iterative methods.
Solution Approach 2:
The patent performs preliminary setup of control parameters and configuration data before the iterative computation begins. By pre-configuring the system with necessary parameters such as rotation angles and stage counts, the actual iterative computation can proceed more efficiently without additional setup overhead during execution, mitigating the time loss inherent in iterative processes.
Data Source
AI summary
A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.