Pipelined Vectoring-Mode CORDIC for Silicon Area Efficiency
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Solution Overview
Problem
Existing Coordinate Rotation Digital Computer (CORDIC) implementations are not computationally efficient and compact, especially in systems with limited hardware resources where a hardware multiplier is not available.
Innovation Solution
A pipelined vectoring-mode CORDIC design that includes a coordinate converter, a series of vector rotators, and at least one lookup table to optimize pre-processing of vector coordinates and reduce hardware resource usage, implemented in a very large scale integration (VLSI) circuit for high throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a traditional CORDIC implementation is used, then mathematical operations can be performed without a hardware multiplier, but the device occupies larger silicon area and has lower computational efficiency
Solution Approach 1:
The CORDIC device is divided into multiple pipeline stages, where each stage performs a specific iteration of the CORDIC algorithm. This segmentation allows parallel processing of multiple operations and improves computational throughput while optimizing the use of hardware resources, thereby achieving better computational efficiency with reduced silicon area utilization.
Solution Approach 2:
The pipeline stages are pre-configured with specific rotation angles and control logic for each iteration. By pre-establishing the computational path and control signals for each stage, the device eliminates the need for dynamic resource allocation during operation, improving computational efficiency while reducing the overall hardware footprint.
2Productivity
If a traditional CORDIC implementation is used, then the device can operate in systems with limited hardware resources, but the throughput is low and computational efficiency is poor
Solution Approach 1:
The CORDIC device is divided into multiple pipeline stages, where each stage performs a specific iteration of the CORDIC algorithm. This segmentation allows parallel processing of multiple operations and improves computational throughput while optimizing the use of hardware resources, thereby achieving better computational efficiency with reduced silicon area utilization.
Solution Approach 2:
The pipeline architecture enables continuous operation by allowing different stages to work on different data simultaneously. While one stage is processing data for the current iteration, another stage is already preparing for the next iteration, ensuring continuous useful action and high throughput without requiring additional hardware resources.
3Productivity
If the CORDIC is implemented with a pipeline structure, then high throughput is achieved, but hardware resources are consumed
Solution Approach 1:
The CORDIC device is divided into multiple pipeline stages, where each stage performs a specific iteration of the CORDIC algorithm. This segmentation allows parallel processing of multiple operations and improves computational throughput while optimizing the use of hardware resources, thereby achieving better computational efficiency with reduced silicon area utilization.
Solution Approach 2:
Each pipeline stage is designed to be multi-functional, handling both the computational logic and control signals for its specific iteration. This universality allows the same hardware structure to be reused across multiple stages, achieving high throughput through parallelism while minimizing the total silicon area required compared to having separate dedicated circuits for each function.
Data Source
AI summary
Various embodiments of the present invention provide pipelined vectoring-mode CORDICS including a coordinate converter operable to yield a converted vector based on an input vector, wherein an x coordinate value of the converted vector is positive, a y coordinate value of the converted vector is positive, and the x coordinate value is greater than or equal to the y coordinate value, a pipeline of vector rotators operable to perform a series of successive rotations of the converted vector to yield a rotated vector and to store rotation directions of the series of successive rotations, and at least one lookup table operable to yield an angle of rotation based on the rotation directions.