Pipelined CRC Engine Layout for High-Speed Timing and Area Limits
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Solution Overview
Problem
Existing CRC engine systems for high-speed serial communication protocols face challenges in optimizing silicon resources and meeting timing requirements, especially as line rates increase and the number of lanes grows, leading to resource bottlenecks and area utilization issues.
Innovation Solution
A CRC engine system is designed with a reduced number of CRC engines arranged in two columns, where the first column processes data from 1 byte to n/2 bytes and the second column processes n/2 bytes, enabling a multiplexer to combine partial results for a complete CRC calculation, thereby reducing resource usage and improving timing optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of CRC engines is increased to handle higher data widths (e.g., 64 bits), then the CRC calculation capability is improved, but the silicon area utilization increases and timing requirements become harder to meet
Solution Approach 1:
The patent divides the CRC calculation into multiple stages using a pipeline architecture. Instead of using a single large CRC engine, the system segments the calculation across multiple smaller CRC engines operating in parallel stages, where each stage processes a portion of the data width (e.g., 32-bit stages for 64-bit CRC). This segmentation reduces the area required per engine while maintaining the overall calculation capability.
Solution Approach 2:
The patent transitions from a single-dimensional approach (one large CRC engine) to a multi-dimensional pipeline structure. By organizing CRC engines in sequential stages that process data in a pipelined manner, the system achieves higher throughput and calculation capability without proportionally increasing silicon area, as multiple engines share resources across different time cycles.
2Productivity
If the line rate or link speed is increased to improve data transmission speed, then the productivity is improved, but the timing requirements for on-chip CRC become increasingly difficult to meet
Solution Approach 1:
The patent implements a pipelined CRC calculation system where multiple CRC engines operate in periodic stages. Each engine processes data at optimized intervals, allowing the system to maintain high throughput by continuously flowing data through different pipeline stages rather than completing entire CRC calculations in single monolithic steps. This periodic multi-stage processing meets stringent timing requirements at high line rates.
3Productivity
If the number of lanes is increased to handle higher data throughput, then the productivity is improved, but the resource count for implementing CRC on-chip increases creating bottlenecks in silicon area and timing
Solution Approach 1:
The patent designs CRC engines with universal functionality that can handle multiple data widths and lane configurations. The same CRC engine architecture can be configured to process different bit widths (32-bit, 64-bit, etc.) and can be reused across multiple lanes through the pipelined structure, reducing the need for separate dedicated engines for each lane and data width combination.
Data Source
AI summary
A cyclic redundancy check (CRC) system includes an input unit, a plurality of CRC engines for 1 byte to n/2 byte, and an output unit. The input unit has a data de-multiplexer for receiving n byte data. The plurality of CRC engines for 1 byte to n/2 byte are connected to the data de-multiplexer for processing demultiplexed n byte data. The output unit has a data multiplexer for providing processed CRC output data. The plurality of CRC engines for 1 byte to n/2 byte are arranged in two columns. A first column includes one or more CRC engines for 1 byte to n/2 byte and a second column includes a CRC engine for n/2 byte.