Pipelined Cryptographic Processor for Faster FHE Ciphertext Operations
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Solution Overview
Problem
Fully homomorphic encryption (FHE) operations involving encrypted data are computation-intensive, making them inefficient for cloud-based computing environments.
Innovation Solution
A cryptographic processor with pipelined modules for ciphertext processing, including on-chip memory and multiple stages that perform operations like multiplication, rotation, and addition in a fully-pipelined manner, reducing processing time by employing multiple stages that cooperate with on-chip memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fully homomorphic encryption operations are performed on encrypted data, then data privacy is preserved, but processing time increases significantly
Solution Approach 1:
The cryptographic processor divides ciphertext processing into multiple pipeline stages, where each stage performs a specific operation (e.g., NTT transformation, multiplication, addition) on portions of the encrypted data. This segmentation allows parallel processing of different ciphertext elements simultaneously, reducing overall processing time while maintaining encryption security.
Solution Approach 2:
The processor pre-loads constants and parameters into on-chip memory before ciphertext processing begins. This preliminary action eliminates the need for repeated memory accesses during the actual computation, significantly reducing processing latency while preserving the encrypted nature of the data throughout the computation.
2Productivity
If multiple pipeline stages are used for ciphertext processing, then processing throughput increases, but device complexity increases
Solution Approach 1:
The cryptographic processor employs a universal pipeline stage design where each stage can handle multiple types of homomorphic operations (addition, multiplication, rotation) through configurable parameters. This multi-functionality allows the same hardware structure to process different ciphertext operations without requiring separate dedicated circuits for each operation type, thus increasing throughput without proportionally increasing complexity.
Solution Approach 2:
The processor implements nested pipeline structures where smaller functional units are embedded within larger processing stages. For example, NTT transformation units are nested within multiplication stages, which are themselves nested within the overall ciphertext processing pipeline. This nesting allows efficient resource utilization and reduces the total number of components needed compared to a fully expanded parallel architecture.
3Speed
If on-chip memory is used for storing constants and ciphertext data, then access speed increases, but chip area increases
Solution Approach 1:
The cryptographic processor implements a hierarchical memory architecture where frequently accessed constants and parameters are stored in small, fast on-chip memory buffers located directly within the pipeline stages. Less frequently accessed data remains in external memory. This local quality approach ensures that critical data access operations occur at high speed while minimizing the total on-chip memory area required.
Solution Approach 2:
The processor loads only the specific constants and parameters needed for the current ciphertext operation into on-chip memory, rather than pre-loading all possible data. This partial action approach reduces on-chip memory requirements while maintaining fast access speeds for the actually used data, balancing area consumption against access performance.
Data Source
AI summary
Cryptographic processor chips, systems and associated methods are disclosed. In one embodiment, a cryptographic processor is disclosed. The cryptographic processor includes a first cryptographic processing module to perform a first logic operation. The first cryptographic processing module includes first input circuitry to receive ciphertext input symbols. A first pipeline stage performs a first operation on the ciphertext input symbols and generates a first stage output. On-chip memory temporarily stores the first stage output and feeds the first stage output to a second pipeline stage in a pipelined manner. The second pipeline stage is configured to perform a second operation on the first stage output in a pipelined manner with respect to the first pipeline stage.