Pipelined Data Transfer Logic With Ready-Signal Hold Registers
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Solution Overview
Problem
Existing configurable logic systems face challenges in achieving timing closure and bandwidth performance due to long paths for ready signals routed through multiple pipelines, which can be exacerbated by the use of holding registers and complex control finite-state machines.
Innovation Solution
A configurable logic system with registers and control logic that enable data transfer between master and slave on a single clock cycle, using hold registers to manage ready signals and multiplexers to optimize data flow, allowing for high-speed timing closure without bandwidth degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ready signal is routed through multiple pipeline stages, then data transfer completeness is ensured, but timing closure becomes difficult due to substantially long path delay
Solution Approach 1:
The patent segments the ready signal path by introducing a hold register that separates the ready signal generation at the slave from its consumption at the master. This segmentation breaks the long combinational path into manageable segments, ensuring data transfer completeness while reducing timing closure difficulty by limiting the signal path to registered stages only.
Solution Approach 2:
The hold register acts as an intermediary element between the slave's ready signal output and the master's ready signal input. This intermediary captures the ready signal at one clock cycle and holds it for the next clock cycle, mediating the timing relationship between master and slave without requiring complex multi-stage pipelining.
2Loss of time
If holding register is added to reduce fanout of ready signal, then timing closure is eased, but device complexity increases due to complicated control FSM
Solution Approach 1:
The patent extracts the timing management function from complex control FSM logic and consolidates it into a simple hold register. By taking out the timing control functionality and implementing it through a dedicated register element rather than complex combinatorial logic, the device complexity is reduced while maintaining timing closure capability.
Solution Approach 2:
The invention changes the parameter of control logic complexity from high (complicated FSM) to low (simple register enable logic). By transforming the control mechanism from a complex state machine to a simple registered enable signal, the device complexity is significantly reduced while the timing closure function is preserved through the hold register's clocked operation.
3Productivity
If data is held in register when ready signal is de-asserted, then bandwidth performance is maintained, but area increases due to additional register resources
Solution Approach 1:
The hold register serves multiple functions: it acts as a data buffer to maintain bandwidth performance, a timing element to capture the ready signal, and a control element to enable/disable data transfer based on the ready signal state. By making this single register multi-functional, the patent maintains bandwidth performance without proportionally increasing the area cost of additional dedicated buffers.
Data Source
AI summary
The present invention relates to a configurable logic system (101) programmed to model a logic design for data pipeline between master and slave; and the method of implementation, wherein said system (101) comprises of at least one first register (112) configured to store and transfer at least one data from said master to said slave; wherein said system (101) is configured to operate on one clock and one reset. The system (101) further comprises of at least one first control logic (118) that controls said first register (112) and fourth register (109) to provide hold to the ready signal from the slave to ease timing closure at high speed.