Pipelined Decoder Memory Layout for HARQ and CRC Bit Storage
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Solution Overview
Problem
Pipelined decoders in wireless communication systems face challenges in managing memory and data traffic due to concurrent HARQ combining and FEC decoding operations, which makes it difficult to store soft bits and hard bits effectively, especially when CRC failures occur, leading to overwritten LLRs and increased memory requirements.
Innovation Solution
A pipelined decoder architecture that uses cyclically selected memory locations to store soft bits and decodes them based on the previous memory location, allowing concurrent operations of HARQ combining and FEC decoding, and stores LLRs and hard bits appropriately to avoid overwriting, with a processing unit handling external memory storage for CRC failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent HARQ combining and FEC decoding operations are performed in pipelined architecture, then processing speed and productivity are improved, but memory requirements and data traffic increase significantly
Solution Approach 1:
The decoder is divided into multiple processing stages (HARQ combining stage, FEC decoding stage, CRC checking stage) that operate concurrently on different code blocks. Each stage processes a specific portion of the workflow, allowing parallel execution without requiring all data to be held in memory simultaneously. This segmentation enables pipelined processing where Stage 1 works on CB1 while Stage 2 works on CB2, reducing peak memory requirements.
Solution Approach 2:
The patent introduces a temporal dimension to the processing architecture by implementing a pipelined multi-stage structure. Instead of sequential processing where one operation completes before the next begins, the system adds a time-based layer where multiple operations progress simultaneously at different stages. This dimensional transformation allows the system to achieve higher throughput without proportionally increasing memory capacity.
2Quantity of substance
If sequential processing is used to determine storage location, then memory usage is reduced, but processing speed and concurrency are lost
Solution Approach 1:
The system pre-allocates specific memory locations for each code block before processing begins. The memory address for storing LLRs or decoded data is determined in advance based on the code block identifier, eliminating the need for sequential search or dynamic allocation during processing. This preliminary assignment of storage locations enables concurrent access patterns without memory conflicts.
Solution Approach 2:
Each code block independently determines its own storage location based on its identifier and the current pipeline stage. The system does not require centralized control or sequential coordination for memory management. Each processing element can autonomously write to or read from its designated memory location, enabling parallel operations without interdependence that would require sequential execution.
Data Source
AI summary
A pipelined decoder for storaging of soft bits and hard bits associated with code blocks of a transmission.The proposed circuit reduces the amount of memory needed at the receiver level for soft bits and hard bits, in a pipelined decoder. Namely, with the solution of the subject application, both the LLRs and hard bits associated with a given code block are available when the CRC value is determined. Hence, the effect obtained non-pipelined decoder is achieved by the pipelined decoder of the subject application. A receiver for a wireless communication system, a method and a computer program are also disclosed.