Pipelined Delta-Sigma ADC Quantization for High Resolution
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Solution Overview
Problem
Existing analog-to-digital converters face challenges in achieving high resolution and high sampling rates while maintaining low power consumption and cost, particularly in portable devices, due to the complexity and instability issues associated with multi-bit delta-sigma modulators.
Innovation Solution
The solution involves cascading first-stage delta-sigma modulation with pipelined noise-shaped second-stage quantization, utilizing a one-bit analog-to-digital converter in a feedforward path and a one-bit digital-to-analog converter in a feedback path, along with multi-stage delta-sigma modulators for less significant bits, to achieve high resolution at wide bandwidths with minimal signal processing delay and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-bit quantization is employed in a delta-sigma loop to achieve high resolution, then conversion resolution is improved, but device complexity grows exponentially because flash type component count is proportional to 2^N
Solution Approach 1:
The patent divides the conversion process into multiple stages: a first delta-sigma modulator stage that processes the input signal and produces a first digital output, followed by a second delta-sigma modulator stage that processes the first digital output to produce a second digital output. This segmentation allows high resolution to be achieved through cascaded lower-resolution stages rather than a single high-resolution flash converter, thereby reducing component count from exponential to linear growth with resolution.
2Speed
If flash type ADC is used for rapid conversion within one clock cycle, then conversion speed is improved, but device complexity grows exponentially with resolution
Solution Approach 1:
The conversion process is segmented into multiple clock cycles distributed across two delta-sigma modulator stages. The first stage operates for a first number of clock cycles to produce an intermediate digital output, which is then processed by the second stage for a second number of clock cycles. This temporal segmentation replaces the spatial explosion of flash comparator arrays with a sequential processing approach that achieves comparable conversion speed without exponential complexity growth.
3Measurement precision
If arbitrarily increasing the order of the modulator is done to achieve high resolution, then conversion resolution is improved, but modulator instability occurs
Solution Approach 1:
Instead of using a single high-order modulator that risks instability, the patent segments the high-order conversion function into two separate lower-order delta-sigma modulator stages. Each stage operates at a manageable order with inherent stability, and their cascaded combination achieves the equivalent of high-order resolution. This segmentation distributes the stability requirements across multiple stable stages rather than concentrating them in one potentially unstable high-order system.
4Measurement precision
If high conversion resolution is achieved, then measurement precision is improved, but sampling rate must be reduced
Solution Approach 1:
The patent segments the high-resolution conversion task into two parallel digital processing paths: the first delta-sigma modulator produces a first digital output at a first sampling rate, and the second delta-sigma modulator produces a second digital output at a second sampling rate. The outputs are combined to achieve high resolution while maintaining high sampling rates in both stages, unlike traditional approaches where increasing resolution forces a reduction in sampling rate.
Data Source
AI summary
A cascaded analog-to-digital converter includes a first stage delta-sigma modulator to quantize an input signal and produce a first quantization error signal. A second, coupled multi-stage delta-sigma modulator quantizes less significant bits of the input signal, wherein a first quantization stage is coupled to the first quantization error signal to quantize the next most significant bits of the input signal and produce a second quantization error signal. A second quantization stage is coupled to the second quantization error signal to quantize the least significant bits of the input signal and produce a third quantization error signal. A noise-shaping filter is coupled to the third quantization error signal, the output of which is subtracted from the first quantization error signal to produce said input of the first quantization stage.