Pipelined Erasure Generation for Memory-Efficient MPE-FEC Decoding
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Solution Overview
Problem
In digital video broadcasting (DVB) systems, especially in mobile devices with limited resources, the existing MPE-FEC decoders require significant memory for storing erasure information, leading to increased die area and device costs due to the need for storing an additional bit per byte of MPE frame memory, which is not efficiently utilized for error correction.
Innovation Solution
A memory-efficient MPE-FEC decoder design that records error information in a compressed format using error descriptors, allowing for pipelined erasure bit generation and Reed-Solomon decoding, reducing memory requirements by using a fraction of the storage needed for individual erasure bits and enabling row-by-row processing of RS codewords.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual erasure bits are stored for each byte of MPE frame memory, then error correction capability is maintained, but memory requirements and die area increase significantly
Solution Approach 1:
The patent segments the MPE frame memory into rows, where each row contains a codeword and its corresponding erasure bits are generated and processed in a pipelined manner. This segmentation allows the system to handle error correction for one row at a time, reducing the need for storing all erasure bits simultaneously in memory.
Solution Approach 2:
The patent introduces an erasure generator as an intermediary component that produces erasure bits on-demand during the decoding process. Instead of pre-storing all erasure bits in memory, the erasure generator creates them as needed and feeds them to the Reed-Solomon decoder, acting as a mediator between the MPE frame memory and the decoder.
2Reliability
If significant memory is allocated for storing erasure information, then error correction can be performed, but device costs and complexity increase
Solution Approach 1:
The patent performs preliminary actions by generating erasure bits in advance for each row before the Reed-Solomon decoding operation. The erasure generator is configured to produce the necessary erasure information proactively, allowing the decoder to receive ready-to-use data without requiring extensive memory storage or complex random access mechanisms.
Solution Approach 2:
The patent implements a continuous pipelined operation where the erasure generator and Reed-Solomon decoder work in tandem. As the decoder processes one row, the erasure generator simultaneously prepares erasure bits for the next row, ensuring continuous useful action without idle periods or the need for large memory buffers to hold intermediate data.
3Area of stationary object
If memory is reduced by using compressed error descriptors, then die area decreases, but processing complexity increases
Solution Approach 1:
The patent changes the parameter representation from storing full erasure bit sequences to using compressed error descriptors that indicate error patterns with fewer bits. This parameter change reduces memory requirements while the added processing complexity is localized to the erasure generator, which can efficiently expand these descriptors into the actual erasure bits needed for decoding.
Data Source
AI summary
A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof. Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values.